howard@metheus.UUCP (Howard A. Landman) (08/10/84)
I am looking for a technical leadership role in the general area of IC design and CAD software development. This means that I want to BOTH be involved in designing ICs or helping others to design ICs, AND building CAD tools to improve the design process. Startups are especially welcome. Please contact me at home at (503) 640-6625 or via U.S. Mail at 725 E. Main, Hillsboro OR 97123, as my net address may shortly vanish. A two-page resume follows in "vtroff -me" format: -------------------------------CUT-HERE---------------------------------------- .ce 2 .sz 12 .b Howard A. Landman .br .i VLSI Designer and CAD Programmer .sz 10 .sp 2 .uh Education .ip MS Computer Science, University of California, Berkeley, 6/82 .ip BA Mathematics (with honors), University of California, Berkeley, 8/73 .uh Experience .lp .(b L .r 6/82 to present: .i VLSI/CAD Designer .r Metheus Corporation, Hillsboro, OR .)b .ip Principal software engineer for 10 programs included in Metheus' CAE workstation; also contributed to several other programs. All work in C under UNIX on VAX or 68000. Supervised one programmer. Negotiated with foundries such as AMI and IMP, leading to technology exchange agreements. Several months of technical marketing work including much travel. .lp .(b L 6/81 to 6/82: .i Director of Software Engineering .r SynMos Corporation, Palo Alto, CA .)b .ip Developed and maintained CAD environment for IC design, including configuration of mainframe and workstations and integration of software packages. Managed software developers. Helped teach introductory VLSI design courses. Provided design assistance service to customers. Designed test patterns and circuits to evaluate fabrication quality, and screened incoming wafers. Designed standard library cells for use in classes. .lp .(b L 1979 to 1981: .i Research Intern .r Xerox Corporation, Palo Alto Research Center, Palo Alto, CA .)b .ip Enhanced and maintained interactive text/graphics system for managing process and run data for NMOS fabrication facility. Designed circuits and test patterns for process characterization. .lp .(b L 1978 to 1979: .i Systems Engineer .r Fujitsu Limited, Sunnyvale, CA .)b .ip Surveyed various aspects of U.S. computer industry. Gathered information from literature and other sources. Attended conferences and lectures. Analyzed data and prepared reports for home offices in Japan. .lp .(b L 1976 to 1978: .i Business Planner, Financial Systems Analyst .r Amdahl Corporation, Sunnyvale, CA .)b .ip Studied computer software vendors and market in relation to corporate strategy. Identified and evaluated acquisition candidates, products, technical expertise. Prepared 200 page report of findings. Presented recommendations to corporate officers. Supervised two employees. Interfaced with programmers and vendors for selection, design, implementation and evaluation of accounting programs. .lp .(b L .i Process Computer Analyst .r General Electric Co., Nuclear Energy Division, San Jose, CA .)b .ip Helped develop a fast approximation scheme for neutron flux in reactor cores, and test it against detailed simulations. Techniques included pattern recognition, linear regression, and symmetry group theory. .lp .(b L .i Teaching Assistant .r University of California, Computer Science Division, Berkeley CA .)b .ip Twice assisted in teaching VLSI design course. Counseled students on use of CAD tools, good design practices, and other issues related to design of NMOS ICs. Coordinated submission of completed chips for fabrication. .uh Publications: .ip "OPUSI: An Optical Digital Position Sensor", .i ICCAD 83 Digest of Technical Papers, .r September 1983 .ip "Integrating Foundry Processes into the Engineering Workstation", .i Electro/83 Professional Program, .r April 1983 .ip .i Automatic Layout of Optimized PLA Structures, .r Master's Thesis & ERL Memo, U.C. Berkeley, 1982 .ip "PLA Tools", in .i Berkeley VLSI Tools, .r Bob Mayo (ed.), Computer Science Division, U.C. Berkeley, 1982 .ip "A RISCy Approach to VLSI", .i VLSI Design, .r 4th quarter 1981 .ip "VLSI Implementations of a Reduced Instruction Set Computer", .i CMU Conference on VLSI Systems and Computations, .r 1981 .uh "Chips designed:" .ip .i HORUS boustrophedon: .r Unusual analog position sensor using coupled light-controlled oscillators and switched capacitor. 44 FETs. (in fab) .ip .i OPUSI: .r A digital position sensor incorporating 256 photodiodes and 69,000 FETs on a single chip. Extremely regular design. (worked on first fab at both 4um and 3um) .ip .i RISC: .r Reduced Instruction Set Computer (with many other designers). 44,000 FETs. (worked on first good fab) .ip .i XIB: .r X-Port Input Buffer (with Ion Ratiu and Joe Decuir). Multi channel inchworm FIFO for the X-Tree project. Included on-chip error correction (SEC/DED). 5,000 FETs. .ip .i XHEC: .r Hamming Encoder/Decoder/Corrector for XIB (with Ion Ratiu). .ip .i XFIFO: .r Single FIFO cell for XIB. .ip .i RPLA: .r Reprogrammable Logic Array. .ip .i TALLY: .r Implementation of Mead-Conway Tally Circuit. (worked on first fab) .ip .i SynMosTP: .r Wafer acceptance test pattern for SynMos Corp. .ip .i TP1180, TP780, TP580, TP380: .r Test patterns for Xerox PARC fab line. .uh Interests: .ip Go, Aikido, Tai Chi, music (guitar, synthesizer), mountaineering, backgammon, jogging -------------------------------CUT-HERE----------------------------------------
howard@metheus.UUCP (08/13/84)
Several people who don't have Versatecs or vtroff have asked for a more
readable version of the resume I posted three days ago. Here it is, using
only one convention which isn't totally vanilla, namely, that underscore
followed by backspace followed by a letter means to display that letter
underlined. This will work with most printers and some terminals, and is
handled correctly by such software as "more". If you can't parse it, just
delete all underscore-backspace pairs. Two minor errors have also been fixed.
Please refer to the previous submission for a description of my job goals.
_H_o_w_a_r_d _A. _L_a_n_d_m_a_n
_V_L_S_I _D_e_s_i_g_n_e_r _a_n_d _C_A_D _P_r_o_g_r_a_m_m_e_r
_E_d_u_c_a_t_i_o_n
MS Computer Science, University of California, Berke-
ley, 6/82
BA Mathematics (with honors), University of California,
Berkeley, 8/73
_E_x_p_e_r_i_e_n_c_e
6/82 to present:
_V_L_S_I/_C_A_D _D_e_s_i_g_n_e_r
Metheus Corporation, Hillsboro, OR
Principal software engineer for 10 programs included in
Metheus' CAE workstation; also contributed to several
other programs. All work in C under UNIX on VAX or
68000. Supervised two programmers. Negotiated with
foundries such as AMI and IMP, leading to technology
exchange agreements. Several months of technical mark-
eting work including much travel.
6/81 to 6/82:
_D_i_r_e_c_t_o_r _o_f _S_o_f_t_w_a_r_e _E_n_g_i_n_e_e_r_i_n_g
SynMos Corporation, Palo Alto, CA
Developed and maintained CAD environment for IC design,
including configuration of mainframe and workstations
and integration of software packages. Managed software
developers. Helped teach introductory VLSI design
courses. Provided design assistance service to custo-
mers. Designed test patterns and circuits to evaluate
fabrication quality, and screened incoming wafers.
Designed standard library cells for use in classes.
1979 to 1981:
_R_e_s_e_a_r_c_h _I_n_t_e_r_n
Xerox Corporation, Palo Alto Research Center, Palo Alto, CA
Enhanced and maintained interactive text/graphics sys-
tem for managing process and run data for NMOS fabrica-
tion facility. Designed circuits and test patterns for
process characterization.
1978 to 1979:
_S_y_s_t_e_m_s _E_n_g_i_n_e_e_r
Fujitsu Limited, Sunnyvale, CA
Surveyed various aspects of U.S. computer industry.
Gathered information from literature and other sources.
Attended conferences and lectures. Analyzed data and
prepared reports for home offices in Japan.
1976 to 1978:
_B_u_s_i_n_e_s_s _P_l_a_n_n_e_r, _F_i_n_a_n_c_i_a_l _S_y_s_t_e_m_s _A_n_a_l_y_s_t
Amdahl Corporation, Sunnyvale, CA
Studied computer software vendors and market in rela-
tion to corporate strategy. Identified and evaluated
acquisition candidates, products, technical expertise.
Prepared 200 page report of findings. Presented recom-
mendations to corporate officers. Supervised two
employees. Interfaced with programmers and vendors for
selection, design, implementation and evaluation of
accounting programs.
Summer 1974:
_P_r_o_c_e_s_s _C_o_m_p_u_t_e_r _A_n_a_l_y_s_t
General Electric Co., Nuclear Energy Division, San Jose, CA
Helped develop a fast approximation scheme for neutron
flux in reactor cores, and test it against detailed
simulations. Techniques included pattern recognition,
linear regression, and symmetry group theory.
_T_e_a_c_h_i_n_g _A_s_s_i_s_t_a_n_t
University of California, Computer Science Division, Berkeley CA
Twice assisted in teaching VLSI design course. Coun-
seled students on use of CAD tools, good design prac-
tices, and other issues related to design of NMOS ICs.
Coordinated submission of completed chips for fabrica-
tion.
_P_u_b_l_i_c_a_t_i_o_n_s:
"OPUSI: An Optical Digital Position Sensor", _I_C_C_A_D _8_3
_D_i_g_e_s_t _o_f _T_e_c_h_n_i_c_a_l _P_a_p_e_r_s, September 1983
"Integrating Foundry Processes into the Engineering
Workstation", _E_l_e_c_t_r_o/_8_3 _P_r_o_f_e_s_s_i_o_n_a_l _P_r_o_g_r_a_m, April
1983
_A_u_t_o_m_a_t_i_c _L_a_y_o_u_t _o_f _O_p_t_i_m_i_z_e_d _P_L_A _S_t_r_u_c_t_u_r_e_s, Master's
Thesis & ERL Memo, U.C. Berkeley, 1982
"PLA Tools", in _B_e_r_k_e_l_e_y _V_L_S_I _T_o_o_l_s, Bob Mayo (ed.),
Computer Science Division, U.C. Berkeley, 1982
"A RISCy Approach to VLSI", _V_L_S_I _D_e_s_i_g_n, 4th quarter
1981
"VLSI Implementations of a Reduced Instruction Set Com-
puter", _C_M_U _C_o_n_f_e_r_e_n_c_e _o_n _V_L_S_I _S_y_s_t_e_m_s _a_n_d _C_o_m_p_u_t_a_-
_t_i_o_n_s, 1981
_C_h_i_p_s _d_e_s_i_g_n_e_d:
_H_O_R_U_S _b_o_u_s_t_r_o_p_h_e_d_o_n: Unusual analog position sensor
using coupled light-controlled oscillators and switched
capacitor. 44 FETs. (in fab)
_O_P_U_S_I: A digital position sensor incorporating 256 pho-
todiodes and 69,000 FETs on a single chip. Extremely
regular design. (worked on first fab at both 4um and
3um)
_R_I_S_C: Reduced Instruction Set Computer (with many other
designers). 44,000 FETs. (worked on first good fab)
_X_I_B: X-Port Input Buffer (with Ion Ratiu and Joe
Decuir). Multi channel inchworm FIFO for the X-Tree
project. Included on-chip error correction (SEC/DED).
5,000 FETs.
_X_H_E_C: Hamming Encoder/Decoder/Corrector for XIB (with
Ion Ratiu).
_X_F_I_F_O: Single FIFO cell for XIB.
_R_P_L_A: Reprogrammable Logic Array.
_T_A_L_L_Y: Implementation of Mead-Conway Tally Circuit.
(worked on first fab)
_S_y_n_M_o_s_T_P: Wafer acceptance test pattern for SynMos
Corp.
_T_P_1_1_8_0, _T_P_7_8_0, _T_P_5_8_0, _T_P_3_8_0: Test patterns for Xerox
PARC fab line.
_I_n_t_e_r_e_s_t_s:
Go, Aikido, Tai Chi, music (guitar, synthesizer), moun-
taineering, backgammon, jogging