mazum@alberta.UUCP (Pinaki Mazumder) (10/13/84)
I shall be finishing my MSc in Computing Science by the end of
October, 1984. Immediately I am looking for a job in the industry
or in the university. If you have anything to offer, please
communicate to me through the net, the phone or the letter. I am
forwarding my Resume for your perusal:
RESUME
Name: Pinaki Mazumder
Date of Birth: July 04, 1954.
Address: 214-B Michiner Park, Edmonton, Alberta, Canada, T6H
4M5.
Electronic mail address: alberta!mazum
Phone No: Residence: 403-434-8281, Office: 403-432-5198 and
403-432-2766
Professional Experience:-
(1) Teaching Experience: Have been working as a Teaching Assistant
and Research Assistant in the University of Alberta from Sept,
1982. Worked as TA in the follwing courses:
i) Mini & Micro Computer Architecture
ii) Programming in High Level languages
iii) Switching Theory
iv) Telecommunications and Data Communications
(2) Software Knowledge: I am conversant with the following
machines: IBM 360/44, Amdahl 580/5860, VAX 11/780 and micros.
I have been using UNIX and MTS OS. I have used UNIX systems
for simulation, troffing (with preprocessors) and graphics work
of my thesis. UNIX has been implemented over the VAX machines
(4 in number) and SUN and JUPITER workstations in our depart-
ment. I have extensively used them during my thesis and other
course work. I am having programming experience with the follo-
wing languages: C, LISP, PASCAL, FORTRAN 77 and other special
purpose simulation and VLSI layout languages (like SPICE, KIC,
etc.).
(3) Industrial Experience: Worked as a Senior Design Engineer for
six years (1976-1982) at Bharat Electronics Ltd, India. My man-
date was design, development and application of Consumer Elec-
tronics. I was associated with the following projects:
Design of Integrated Circuits:
i) Design of Tape Recorder IC,
ii) Design of LSI for Analog Clock,
iii) Hearind Aid IC,
iv) Vertical Deflection IC,
v) Design of LSI Analog Clock
Application Systems:
i) Design of TV Receiver with 4 ICs,
ii) Design of Tape Recorder using the above IC,
iii) Micro Processor (8085) Based Test Equipments for
Plasma & Flourescent Display.
Publication:
a) Planar Topologies for Quadtree Representation, Congressus
Numeruntium, 14th Annual Conference on Numerical Mathematics
and Computing Science @ University of Manitoba (1984). (also
submitted to Information Pro- cessing Letters)
b) Networks And Embedding Considerations of Nearest Neigh-
borhood Arrays for VLSI Design, Technical Report of Dept. of
Computing Science (also to be submitted to IEEE Transaction
of Computers).
Contributed 4 circuit Application Ideas on the following:
i) Universal seven segment to decimal decoder, ii) IC trio makes
economical divided by 12 counter/decoder, iii) Potless VOLUME
control with visual indicator, iv) Clock chip provides Number
Display in addition to Time Display.
Membership of Professional Organisation: i) Member of IEEE,
USA, ii) Member of Institute of Electronics & Communication
Engineers, India.
Extra Curricular Activity:-
i) Special Awards: a) Won First Prize in all India Technical
Talk Contest (1976), held by Institute of Electronics and
Telecommunication Engineers, India, b) Won First Prize in
all India Essay Contest (1976), held by IETE, India, c) Have
been awarded Yuogoslav Govt. Scholarship for Post Graduate
Study.
ii) Sports:- a) Won the Inter University Badminton Tourna-
ment (Team Event), b) Was Runner Up in Inter Industries Tennis
Tournament (Bangalore), c) Won many medals in Indian Institute
of Science Sports Events.
Name and address of referees:
1) Prof. John Tartar, Dept. of Computing Science, University of
Alberta, Edmonton, Canada, T6G 2H1. Phone: 403-432-5198.
2) Prof. Keith Stromsmoe, Dept. of Electrical Engineering,
University Phone: 403-432-3033. of Alberta, Edmonton, Canada,
T6G 2H1.
3) Prof. Kellog Wilson, Dept. of Computing Science, University
of Alberta, Edmonton, Canada, T6G 2H1. Phone: 403-432-5198.
Educational Qualification:
Degree Year University Result
a) M.Sc. (Computing 1984 Univ. of Alberta, CGPA= 7.7/9.0
Science) Edmonton, Canada.
b) B.E. (Electronics 1976 Indian Institute of CGPA= 3.6/4.0
& Telecommunication) Science, Bangalore Rank= 5th
c) B.Sc. (Physics) 1973 Gauhati Univ, India Marks= 79%
1st Rank in University
d) Pre University 1970 Gauhati Univ, India Marks= 81%
2nd Rank in University
e) H.S.L.C. Exam. 1969 Assam Board, India Marks= 72%
Thesis Topic for MSc: Embedding and Networks Aspects of Cellular
Structures for on-chip Multiprocessing in VLSI.
Courses taken for MSc degree:
1) VLSI Circuit Design
2) Local Area Networks
3) Computer Architectures
4) Computer Hardware
5) Software Engineering
6) Theory of Programming Languages
7) Adaptive Information Processing
8) Analysis of Algorithms
9) Artificial Intelligence
Now attending some Advanced Courses:
1) Advanced Computer Architectures on Fifth Generation Com-
puters
2) Giant Vector Processor
3) Unix Operating Systems
Worked in First Summer on: Local Area Networks.
Project Works done for courses:
1) Resolution Theorem Prover using LISP language
2) Static Data Flow Analysis for Recursive Languages
3) Design, Simulation and Laying out of Universal seven seg-
ment to decimal decoder using SPICE and KIC.
4) Study of Regularity of Interconnection Networks on Chip
Yield in VLSI.
ABSTRACT of the MSc THESIS
The advent of VLSI has opened a new vista for parallel pro-
cessing. On-chip multiprocessing by numerous tiny processors is
envisioned to be the major application goal of the emerging VLSI
and VHSIC technologies.
This thesis attempts to identify the interconnection net-
works and the processor geometries which can be cost-effectively
implemented within the chip for on-chip multiprocessing. The
thesis has proposed a computational model for CMOS VLSI technol-
ogy and has evaluated the existing SIMD interconnection networks
employing the results of the model. The computational model
enumerates the technological, embedding, power dissipation, tim-
ing and failure aspects of VLSI technology. The interconnection
networks have been divided into four topologically equivalent
classes and the merits and demerits of each class have been
perused to reveal the orthogonal aspects of parallel computation
viz., the physical aspects, the computational aspects and the
reliability aspects. Cellular interconnection networks having
uniform and short interconnects have been shown to be the most
suitable candidates for on-chip multiprocessing.
The layout geometry for such networks has been investi-
gated. The traditional shape for the processors is understood
to be a square. The algorithms for transforming a natural lay-
out having a rectangular shape with arbitrary aspect ratio into
a square layout have been constructed. The difficulties and
disadvantages with such post-processing have been studied and an
alternate strategy has been suggested. A number of possible
geometrical shapes for the processors have been identified.
Mosaic layout by cellular structures having a cell geometry
identical to polyominoes has been designed for the square and
the hexagonal array networks. Polyominoes which describe the
fault-tolerant mesh networks have been identified. Embedding
algorithms have been designed to construct such networks with
optimal redundancy. Finally, the chip area, the layout cost and
the computational power of such layout structures have been
analyzed.