page@swan.ulowell.edu (Bob Page) (10/29/88)
Submitted-by: anakin@utcs.toronto.edu (Brad Fowles)
Posting-number: Volume 2, Issue 32
Archive-name: hardware/lucas.3
# This is a shell archive. Remove anything before this line
# then unpack it by saving it in a file and typing "sh file"
# (Files unpacked will be owned by you and have default permissions).
# This archive contains the following files:
# Packaging_List
# Parts_List
# README
# Transactor_Article
# Wiring_List
#
if `test ! -s Packaging_List`
then
echo "writing Packaging_List"
cat > Packaging_List << '\Rogue\Monster\'
%*********************************************************************
% *
% Program : PC-FORM VERSION 3.00 *
% Date : Jul 18 1988 *
% Time : 02:25:46 PM *
% File In : AM20AW27.PNL *
% File Out : AM20AW27.PKL *
% Format : PACKAGING LIST *
% *
%*********************************************************************
U2 ( 1 =BGACK', 2 =DGND, 3 =RESET',
4 =VCC, 5 =FC0, 6 =SIZE0,
7 =, 8 =UN000013, 9 =DSACK1',
10 =DGND, 11 =AS20', 12 =DS20',
13 =D31, 14 =D28, 15 =D25,
16 =D22, 17 =D20, 18 =D17,
19 =DGND, 20 =VCC, 21 =D14,
22 =D12, 23 =D9, 24 =D8,
25 =VCC, 26 =D4, 27 =D2,
28 =D0, 29 =IPL1', 30 =DGND,
31 =VCC, 32 =, 33 =,
34 =A3, 35 =A5, 36 =A6,
37 =A8, 38 =A11, 39 =A14,
40 =DGND, 41 =VCC, 42 =A19,
43 =A22, 44 =A23, 45 =,
46 =, 47 =, 48 =A1,
49 =BG20', 50 =16M, 51 =VCC,
52 =, 53 =FC220, 54 =SIZE1,
55 =AVEC', 56 =BERR', 57 =HALT',
58 =R/W20, 59 =D29, 60 =D26,
61 =D24, 62 =D21, 63 =D18,
64 =D16, 65 =VCC, 66 =D13,
67 =D10, 68 =D6, 69 =D5,
70 =D3, 71 =D1, 72 =IPL0',
73 =IPL2', 74 =DGND, 75 =DGND,
76 =A2, 77 =A4, 78 =A7,
79 =A10, 80 =A13, 81 =A15,
82 =DGND, 83 =A18, 84 =A20,
85 =, 86 =, 87 =,
88 =BR', 89 =, 90 =VCC,
91 =VCC, 92 =FC1, 93 =DBEN',
94 =DSACK0', 95 =DGND, 96 =DGND,
97 =D30, 98 =D27, 99 =D23,
100 =D19, 101 =DGND, 102 =D15,
103 =D11, 104 =D7, 105 =DGND,
106 =VCC, 107 =A9, 108 =A12,
109 =A16, 110 =A17, 111 =A21,
112 =, 113 =, 114 =A0 )
[ FIXED =1 ]
U1 ( 1 =D20, 2 =D19, 3 =D18,
4 =D17, 5 =D16, 6 =UN000021,
7 =UN000022, 8 =UN000023, 9 =UN001020,
10 =DTACK', 11 =BG00', 12 =BGACK',
13 =BR', 14 =VCC, 15 =7M,
16 =DGND, 17 =HALT', 18 =RESET',
19 =VMA', 20 =E, 21 =VPA',
22 =BERR', 23 =IPL2', 24 =IPL1',
25 =IPL0', 26 =FC200, 27 =FC1,
28 =FC0, 29 =A1, 30 =A2,
31 =A3, 32 =A4, 33 =A5,
34 =A6, 35 =A7, 36 =A8,
37 =A9, 38 =A10, 39 =A11,
40 =A12, 41 =A13, 42 =A14,
43 =A15, 44 =A16, 45 =A17,
46 =A18, 47 =A19, 48 =A20,
49 =VCC, 50 =A21, 51 =A22,
52 =A23, 53 =DGND, 54 =D31,
55 =D30, 56 =D29, 57 =D28,
58 =D27, 59 =D26, 60 =D25,
61 =D24, 62 =D23, 63 =D22,
64 =D21 )
U3 ( 1 =VCC, 2 =VCC, 3 =DGND,
4 =RESET', 5 =, 6 =UN001004,
7 =DS20', 8 =AS20', 9 =A3,
10 =A1, 11 =R/W20, 12 =DGND,
13 =CPDSAK1', 14 =D30, 15 =D29,
16 =D27, 17 =D26, 18 =D24,
19 =D22, 20 =D21, 21 =D19,
22 =D18, 23 =D16, 24 =DGND,
25 =D15, 26 =D14, 27 =D11,
28 =DGND, 29 =D8, 30 =D7,
31 =D6, 32 =D4, 33 =D3,
34 =D1, 35 =D0, 36 =DGND,
37 =DGND, 38 =16M, 39 =DGND,
40 =VCC, 41 =DGND, 42 =A4,
43 =A2, 44 =VCC, 45 =CPCS',
46 =CPDSAK0', 47 =D31, 48 =D28,
49 =D25, 50 =DGND, 51 =D23,
52 =DGND, 53 =D20, 54 =D17,
55 =VCC, 56 =D12, 57 =D13,
58 =D10, 59 =VCC, 60 =DGND,
61 =D5, 62 =D2, 63 =,
64 =DGND, 65 =DGND, 66 =UN000025,
67 =VCC, 68 =D9 )
[ FIXED =1 ]
SIP1 ( 1 =VCC, 2 =UN001004, 3 =UN000025,
4 =AVEC', 5 =UN000013, 6 =RESET',
7 =CPDSAK0', 8 =CPDSAK1', 9 =SRDSAK1',
10 =SRDSAK0' )
[ FP =10SIP ]
SIP2 ( 1 =VCC, 2 =, 3 =AS20',
4 =DS20', 5 =, 6 =,
7 =, 8 =, 9 =,
10 = )
[ FP =10SIP ]
R2 ( 1 =R/W00, 2 =UN001020 )
[ FP =RC07 ]
R1 ( 1 =DGND, 2 =16M )
[ FP =RC07 ]
R3 ( 1 =16M, 2 =VCC )
[ FP =RC07 ]
R4 ( 1 =AS00BUF', 2 =UN000021 )
[ FP =RC07 ]
R5 ( 1 =UDS', 2 =UN000022 )
[ FP =RC07 ]
R6 ( 1 =LDS', 2 =UN000023 )
[ FP =RC07 ]
DIN ( 1 =A0, 2 =VCC, 3 =A1,
4 =A2, 5 =VCC, 6 =A3,
7 =A4, 8 =VCC, 9 =A5,
10 =A6, 11 =VCC, 12 =A7,
13 =A8, 14 =VCC, 15 =A9,
16 =A10, 17 =VCC, 18 =A11,
19 =A12, 20 =VCC, 21 =A13,
22 =A14, 23 =16M, 24 =A15,
25 =A16, 26 =VCC, 27 =A17,
28 =A18, 29 =SIZE0, 30 =A19,
31 =A20, 32 =VCC, 33 =A21,
34 =A22, 35 =, 36 =A23,
37 =SIZE1, 38 =VCC, 39 =,
40 =, 41 =AS20', 42 =,
43 =VCC, 44 =VCC, 45 =,
46 =, 47 =DS20', 48 =,
49 =D0, 50 =DGND, 51 =D1,
52 =D2, 53 =R/W20, 54 =D3,
55 =D4, 56 =DGND, 57 =D5,
58 =D6, 59 =DBEN', 60 =D7,
61 =D8, 62 =DGND, 63 =D9,
64 =D10, 65 =SRDSAK0', 66 =D11,
67 =D12, 68 =DGND, 69 =D13,
70 =D14, 71 =SRDSAK1', 72 =D15,
73 =D16, 74 =DGND, 75 =D17,
76 =D18, 77 =DGND, 78 =D19,
79 =D20, 80 =DGND, 81 =D21,
82 =D22, 83 =DGND, 84 =D23,
85 =D24, 86 =DGND, 87 =D25,
88 =D26, 89 =DGND, 90 =D27,
91 =D28, 92 =DGND, 93 =D29,
94 =D30, 95 =DGND, 96 =D31 )
U4 ( 1 =7M', 2 =FC220, 3 =FC1,
4 =FC0, 5 =A19, 6 =A18,
7 =A17, 8 =A16, 9 =VPA',
10 =DGND, 11 =DGND, 12 =Z3',
13 =FC2, 14 =UN002004, 15 =UN000003,
16 =UN000002, 17 =UN000001, 18 =CPCS',
19 =E, 20 =VCC )
[ FP =DIP20 ]
U5 ( 1 =7M, 2 =VPA', 3 =AS20DLY',
4 =UN000001, 5 =UN000002, 6 =UN000003,
7 =UN002004, 8 =BGACK', 9 =BG20',
10 =DGND, 11 =DGND, 12 =AS00',
13 =HIGHZ, 14 =, 15 =,
16 =, 17 =VMA', 18 =AS20',
19 =BG00', 20 =VCC )
[ FP =DIP20 ]
U6 ( 1 =16M, 2 =AS20DLY', 3 =Z3',
4 =VMA', 5 =7M, 6 =DS20DLY',
7 =7ME2, 8 =DTACK', 9 =QUAL',
10 =DGND, 11 =DGND, 12 =,
13 =, 14 =, 15 =QUAL',
16 =, 17 =, 18 =DTTRIG',
19 =, 20 =VCC )
[ FP =DIP20 ]
U8 ( 1 =UN002012, 2 =UN002012, 3 =7M,
4 =VCC, 5 =, 6 =DS20DLY',
7 =DGND, 8 =AS20DLY', 9 =,
10 =VCC, 11 =7M, 12 =UN002011,
13 =UN002011, 14 =VCC )
U9 ( 1 =VCC, 2 =UN002020, 3 =16M,
4 =VCC, 5 =SYSDACK1, 6 =,
7 =DGND, 8 =7ME2, 9 =,
10 =VCC, 11 =7M, 12 =7ME2,
13 =VCC, 14 =VCC )
U11 ( 1 =AS00, 2 =AS00, 3 =UN002018,
4 =VCC, 5 =, 6 =UN002020,
7 =DGND, 8 =, 9 =R/W00,
10 =VCC, 11 =7M, 12 =R/W20,
13 =VCC, 14 =VCC )
U10 ( 1 =7M, 2 =7M', 3 =DS20',
4 =UN002012, 5 =AS20', 6 =UN002011,
7 =DGND, 8 =, 9 =,
10 =AS00, 11 =AS00', 12 =UN002018,
13 =DTTRIG', 14 =VCC )
OSC ( 1 =, 2 =, 3 =,
4 =, 5 =, 6 =A4,
7 =DGND, 8 =16M, 9 =,
10 =, 11 =D15, 12 =,
13 =, 14 =VCC )
[ FIXED =0 ]
U7 ( 1 =HIGHZ, 2 =DS20DLY', 3 =A0,
4 =SIZE0, 5 =SIZE1, 6 =AS20DLY',
7 =CPCS', 8 =CPDSAK0', 9 =SRDSAK0',
10 =DGND, 11 =SYSDACK1, 12 =DSACK0',
13 =SRDSAK1', 14 =DSACK1', 15 =CPDSAK1',
16 =AS00BUF', 17 =AS00', 18 =LDS',
19 =UDS', 20 =VCC )
[ FP =DIP20 ]
J2 ( 1 =FC200, 2 =AVEC' )
[ FP =2STRIP ]
J1 ( 1 =FC220, 2 =FC2 )
[ FP =2STRIP ]
C19 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C7 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C24 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C28 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C31 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C15 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C29 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C5 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C6 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C32 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C25 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C30 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C4 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C13 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C14 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C12 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C16 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C2 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C1 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C27 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C26 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C23 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C3 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C33 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C18 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C22 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C20 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C21 ( 1 =VCC, 2 =DGND )
[ FP =CK06 ]
C17 ( 1 =DGND, 2 =VCC )
[ FP =CK06 ]
C11 ( 1 =DGND, 2 =VCC )
[ FP =CK06 ]
C9 ( 1 =DGND, 2 =VCC )
[ FP =CK06 ]
C8 ( 1 =DGND, 2 =VCC )
[ FP =CK06 ]
C10 ( 1 =DGND, 2 =VCC )
[ FP =CK06 ]
\Rogue\Monster\
else
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fi
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then
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fi
if `test ! -s Parts_List`
then
echo "writing Parts_List"
cat > Parts_List << '\Rogue\Monster\'
Parts List for the Lucas Board
U1 68000 Socket .. for Pin Header
U2 MC68020RC16
U3 MC6888116
U4 PAL 16R4-B2
U5 PAL 16R4-B2
U6 PAL 16R4-B2
U7 PAL 16L8-B2
U8 74F74
U9 74ALS74
U10 74F04
U11 74F74
SIP1 4.7K X 9 SIP
SIP2 4.7K X 9 SIP
OSC 16 Meg Clock Oscillator
R1 330 OHM
R2 30 OHM
R3 220 OHM
R4 30 OHM
R5 30 OHM
R6 30 OHM
C1 10 UF. 25V TANT.
C2 .1 UF MONOLITHIC
C3 .1 UF MONOLITHIC
C4 .1 UF MONOLITHIC
C5 .1 UF MONOLITHIC
C6 .1 UF MONOLITHIC
C7 .1 UF MONOLITHIC
C8 .47 UF MONOLITHIC
C9 .1 UF MONOLITHIC
C10 .47 UF MONOLITHIC
C11 .47 UF MONOLITHIC
C12 .1 UF MONOLITHIC
C13 .1 UF MONOLITHIC
C14 .1 UF MONOLITHIC
C15 .1 UF MONOLITHIC
C16 .1 UF MONOLITHIC
C17 .47 UF MONOLITHIC
C18 .1 UF MONOLITHIC
C19 100 UF TANT
C20 .47 UF MONOLITHIC
C21 .01 UF CERAMIC
C22 .47 UF MONOLITHIC
C23 .1 UF MONOLITHIC
C24 .1 UF MONOLITHIC
C25 10 UF TANT
C26 .1 UF MONOLITHIC
C27 .1 UF MONOLITHIC
C28 .1 UF MONOLITHIC
C29 .1 UF MONOLITHIC
C30 .1 UF MONOLITHIC
C31 .1 UF MONOLITHIC
C32 .1 UF MONOLITHIC
C33 .1 UF MONOLITHIC
DIN 96 PIN DIN CONNECTOR (FEMALE)
PCB LUCAS BOARD REV# 3
2 ROWS 32 X 1, (.7 INCH long) HEADER PINS (SAMTEC) ** See Note **
SOCKETS
1, 114 PIN 68020 Socket
1, 68 PIN 68881 Socket
5, 14 PIN DIP Socket
4, 20 PIN DIP Socket
NOTE: READ the notes in the making it drawer.
\Rogue\Monster\
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fi
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then
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cat > README << '\Rogue\Monster\'
The USENET (comp.sources.amiga) distribution of the LUCAS project is
different than what you'd find on BIX, or get from the author. The
Mandelbrot programs & sources, benchmark programs and the utilities
(SetCPU and DeciGel) were omitted, since they are available elsewhere
and because many people will be grabbing these files only to determine
if they want to build the board.
The Commodore utilities (More and IconX) have likewise been removed,
as well as the copyright notice they required.
In addition, all the ".info" and ".fastdir" files have been removed
from this distribution, and most of the files have been renamed. All
the documentation has been reformatted to fit in 80 columns.
NO INFORMATION WAS CHANGED OR OMITTED.
Brad's comments appear below.
..Bob
(moderator - comp.sources.amiga)
---------------------------------------
************************************************************************
* *
* DISCLAIMER *
* *
* NO REPRESENTATIONS OR WARRANTIES ARE MADE WITH RESPECT TO THE *
* ACCURACY, RELIABILITY, PERFORMANCE OR OPERATION OF THIS *
* DOCUMENTATION OR OF THE LUCAS BOARD ITSELF. TO BE CLEARER, *
* YOU ARE DOING THIS TOTALLY AT YOUR OWN RISK AND THE NATURE OF *
* THIS LEARNING EXPERIENCE WILL BE DIRECTLY PROPORTIONAL TO *
* HOW WELL AND HOW CAREFULLY YOU DO THE WORK. TO BE EVEN MORE *
* PRECISE IF ANYTHING WHATSOEVER HAPPENS IT IS NOT MY RESPONSIBILITY *
* ITS YOURS. *
* *
************************************************************************
Here's a brief discription of what you'll find here.
Transactor_Article is the article I wrote for Transactor. Please
excuse any anacronisms which result from Transactor's current
difficulties.
The file Building is for those who are actually building the Lucas
board. If you're just considering building one, a look through this
file will let you know what you're getting into and what you can
expect to get out of it.
The #?.draw files have the two drawings which comprise the LUCAS
board. They were done using draw plus, and they are included here
in case you wish to make plots or printouts of your own. You'll
have to join the similar draw1 and draw2 files together to get a
complete draw file (they were split for Usenet transmission).
The #?_List files are the PCAD document files. The Net Lists will
help in debugging.
The #?.pld files are the four PAL equations for the pals on the LUCAS
Board.
If you've decided that you would like to build a Lucas Board here's
where and how much.
Bare PCB ............ $40.00
4 Pal set ........... $30.00
Mailing ............. $ 5.00
------
Total ............... $75.00
If both the PCB and the Pals are ordered I'll send along a disk with
the information in the original ARC file (including the stuff omitted
from the Usenet distribution) and it will be updated with any new
information.
Send a cheque or money order made out to Brad Fowles to:
Brad Fowles,
RR#5,
Caledon East,
Ontario, Canada.
LON 1E0
Thanks, and Enjoy
\Rogue\Monster\
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then
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fi
if `test ! -s Transactor_Article`
then
echo "writing Transactor_Article"
cat > Transactor_Article << '\Rogue\Monster\'
68020-68881 PLATFORM BOARD, "LUCAS", FOR THE AMIGA 1000
Most of you in the Amiga community are well aware of the wonderful
software which is available in the Public Domain. As a hardware type I
have often been envious of the ease with which software can be shared
among developers and users alike. Ideas and techniques can be
distributed through BBS networks to the general benefit of all. In
contrast, hardware developers lead a comparitively solitary existance,
the exchange of ideas impeded by economic and logistical problems.
Can there be such a thing as Public Domain Hardware? Obviously no one
can give away printed circuit boards, but perhaps we can do the next
best thing: give away as much information as possible and make bare
PCB's available for as close to cost as shipping allows.
The project is a platform board called LUCAS (Little Ugly Cheap
Accelerator System). which replaces the 68000 in your Amiga 1000.
LUCAS provides greater system performance and allows the use of the
68881 math coprocessor as well as an upgrade path to 32-bit wide
memory.
The board has a 68020 and 68881 running at 16 MHz, and interface logic
(consisting of 4 PALS, 4 discretes, 16 MHz crystal, 2 SIP resistor
paks, and some caps) to transpose 68020 cycles to 68000-like cycles.
LUCAS also has a connector which will allow you, at a future date, to
add 32 bit wide memory. (I'll try and get the fine people at
Transactor to publish a memory board for this system in a few months.)
Transactor magazine has graciously agreed to make available bare
printed circuit boards for this project for $40.00, and the complete 4
PAL set for $30.00. The rest is readily available from local
suppliers. The schematic is published here, as are the PAL equations.
Anyone who wants the film plots or Net Lists so they can adapt the
form factor to the Amiga 500 is welcome to them for whatever it costs
me to get and ship them to you. (PCB design was done using P-Cad on
er... an AT ( ...almost said the I word )).
If you own an Amiga 1000 and you would like to experiment with a 68020
and 68881 combination to improve performance this may be the cheapest
way to get there. Unfortunately the chip set is going to cost you
about $370.00 Canadian. Our aim is to make the rest as cheap as
possible. You should be able to be up and running for under $475.00,
or about three quarters of that if you live in the real world.
There are 3 reasons that I decided to do this project. One, I wanted
one myself and couldn't afford the commercial versions. Two, some
friends of mine who are using SCULPT 3D and ANIMATE from Byte by Byte
(both are available in 68020-68881 versions) needed more horsepower to
render their images fast enough to actually make money at it. Three, I
figured all of us Amiga 1000 owners out there with true hacker's
hearts needed some light in our future since 1 meg. of chip ram ain't.
(Maybe some of those 1000's out there can become dedicated rendering
machines.)
When I started the design of this board I used as a reference an
article from EDN January 9th 1986 pp216-219. While looking at this
design I became aware of an application note from Motorola AN944/D,
"MC68020 AND MC68881 PLATFORM BOARD FOR EVALUATION IN A 16 BIT
SYSTEM". I recommend both these documents, especially the latter, if
you wish a better understanding of how this board works. Unfortunately
it is impossible within a short article such as this one to give more
than a brief overview of how the board works. I will try and highlight
those aspects which are specific to the Amiga, but a thorough
understanding will require some digging on your part. I also recommend
the User's Manuals for the MC68020 and the MC68881 which are available
from Motorola as "MC68020UM/AD" and "MC68881UM/AD" respectively.
O.K. Here is the disclaimer. If you get one of these bare boards and
carefully put it together and then intstall it into your Amiga, you
should have no problem and you'll be up and running in an evening or
two. If you have problems then its up to your ingenuity to solve them.
If you don't have some experience with a soldering iron, please, don't
let this be your debut. I will gladly help anyone with problems. There
are three ways you can get in touch with me, USENET at
anakin@utcs.toronto.edu (Brad Fowles), BIX in the ANAKIN, AMIGA
conference or by regular mail through Transactor. If you do manage get
my phone number you better be able to sweet talk me within 30 seconds.
I hope that if there is sufficient interest out there that local user
groups or individuals will add their help to anyone having problems. I
have no objections should anyone get the bare boards and put them
together and install them for a modest price, but please remember that
the purpose of this is to make these available to end users as cheaply
as possible.
If I haven't scared you off, please read on. If I have, well... so
long, and thanks for all the fish.
Once you get one of the bare boards and procure all the parts, next
follow the enclosed instructions and carefully solder sockets for all
the IC's and the crystal onto the board. Solder the resistor paks and
the capacitors into place. Insert the 64 Pin header for the 68000
socket and solder it in.
Installation is quite simple but should be carefully done. Remove the
plastic cover and the EMI shield from the Amiga base unit. On the
right hand side of the PCB, just beside the Exansion connector, is the
68000 CPU. Gently pry the 68000 out of its socket, and store it on a
piece of styrofoam somewhere safe. Now insert the LUCAS board into the
68000 socket, being careful to insure that all 64 pins are correctly
inserted into the socket. If you want to be real careful remove the
disk drive so you can see better. Watch the ribbon cable for the
internal disk drive as the bends in the cable can make things awkward.
As long as you're careful and don't force anything you should have no
problem. You can do initial tests with the cover off, but once you're
satisfied its working put the base unit with its EMI shield back
together again. That's all there is to it. Your heart can now resume
normal operation.
You don't need to know a great deal about the inner workings of the
LUCAS board to enjoy using it, but for those who would like a better
understanding of the nature of running a 32-bit 68020 in a 16-bit
68000 system please read on and I will explain the key points.
Once the LUCAS board has been installed we essentially have divided
the CPU time into two discrete blocks. One, seemingly operating at
7.16 MHz and synchronous to the special purpose chips responsible for
the video, sound, etc. and two, a 16 megahetz asynchronous system
between the 68020 and 68881 and any possible 32-bit wide memory
connected to the LUCAS bus.
The essential design criteria I used for the board were that it should
be able to run asyncronously to the Amiga clock (so speeds of 16 MHz
or greater could be achieved) and that there be no connection other
than through the 68000 socket (to simplify installation.)
In order to achieve this the board must look like a 68000 (4 clock
standard bus cycle) running at 7.16 MHz when it is running its bus
cycles but when it is doing internal processing or talking to the
MC68881 or future 32 bit wide expansion ram, it should run at the full
16 MHz (3 clock bus cycle).
90% of the problem in making this board work comes down to the problem
of making the 68020 appear exactly like the original 68000 it replaces
as it has been used architecturally in the Amiga, but able to go like
stink when it gets the chance.
The address and data lines are easily implemented as they are
connected directly from the 68020 to the 68000 socket. Note that the
16 data bits are connected to data bits D16 through D31. The upper
eight address bits on the 68020 are simply left unconnected.
I have used the * convention to indicate low true signals for ease in
typesetting the article, i.e., *AS means AS is a low true signal. The
PAL equasions are written in CUPL format so I appologise to all you
PALASM user's.
68020 to 68000 Interface.
The 68000 has an asynchonous bus structure. It asserts Address Strobe
(*AS) to begin a bus cycle then waits for the assertion of *DTACK to
end the cycle. This is usually 4 or 6 cycles, but may be held off by
some peripheral device. The 68020 works much the same way except there
are two *DTACK-like signals, *DSACK0 and *DSACK1. Because the 68020
can address in bytes (8 bits), words (16 bits) and longwords (32 bits)
it must be able to differentiate between them. It does this by use of
its dynamic bus sizing capability. A peripheral responds to a bus
cycle by asserting one or both of the *DSACKx signals which tells the
020 the size of the transfer.
DSACK0 DSACK1 TRANSFER SIZE
0 0 32 bit transfer
1 0 16 bit transfer
0 1 8 bit transfer
1 1 Insert Wait States
Bus cycles on for the Amiga are always 16 bits wide so we will assert
only *DSACK1 when responding to Amiga cycles. When we are running
cycles for the 68881 (FPU) or 32-bit wide ram on the LUCAS board
expansion connector we must assert the appropriate *DSACKx
combination.
In general terms with no wait states the 68000 will run a bus cycle in
4 clock cycles; the 020, however, will run the same bus cycle in 3
clock cycles. To correct this we must delay *AS and *DS (Data Strobe)
from reaching the Amiga until after the rising edge of the S2 phase of
the 7.16 Meg. CPU clock. This is accomplished by the flip-flops U8a
and U8b: inverting *AS from the 020 and using the complementary output
with the flip-flop's reset tied to the inverted *AS will delay *AS the
desired amount and terminate *AS20DLY when the *AS from the 020
terminates. This same technique is used for *DS. This creates the two
timing signals *AS20DLY and *DS20DLY.
Byte addressability on the 68000 is accomplished by the Upper Data
Strobe (*UDS) and the Lower Data Strobe (*LDS). The 020 has only a
single Data Strobe (*DS). It uses a combination of the two SIZE pins
and A0 and A1 to define the tranfer pattern from the 020's internal
multiplexer to the external data bus. (Note: bytes appear on data bits
24-31, words appear on data bits 16-31). It is therefore necessary for
us to create *UDS and *LDS. This is accomplished by the following PAL
equations. Note: The data strobes are not asserted during a
Coprocessor cycle. (CPCS)
!UDS = (!DS20DLY) & (!A0) & (CPCS)
!LDS = (!DS20DLY) & ( SIZ1) & (CPCS)
(!DS20DLY) & (!SIZ0) & (CPCS)
(!DS20DLY) & ( A0 ) & (CPCS)
The 68000 contains logic to support the 6800 family of products, and
the Amiga uses this to interface to the 8250s. We must also emulate
this interface as it is not present on the 020. A secondary clock
called the E clock must be generated. It has a frequency of 1/10th the
CPU clock and has a duty cycle of 60% low and 40% high. This is done
by a decade counter in PAL U4. When running a 6800 family cycle the
Amiga or peripheral generates a Valid peripheral Address signal
(*VPA). The 68000 then syncs itself with the E clock and issues a
Valid Memory Address (*VMA) and ends the cycle on the falling edge of
the E clock. The equation,
!Z3 = !QD #
QC #
QB #
QA ;
on PAL U4 in combination with the equation
!Z1.D = (DS20DLY) & (!Z1) #
(DS20DLY) & ( Z3) & (!VMA);
asserts *DSACK1 in the 9th state of E clock by the generation of the
Z1 signal so that the long VPA, VMA cycle can be terminated correctly.
68020 to 68881 Interface
The MC68881 chip select (*CS) must be decoded from the 020. The 020
generates a 111 on the Function Code pins (CPU Space), a 0010 on the
address lines A16-A19 which means this is a FPU coprocessor cycle, and
a coprocessor ID on Address lines A13-A15. Since there is only one
coprocessor in this design, A13-A15 are undecoded. The rest is decoded
by PAL U4 in the following equation:
CPCS = (FC2)&(FC1)&FC0)&(!A19)&(!A18)&(A17)&(!A16)
This generates the *CS (Chip Select) to the 68881.
Zen and the Art of Cycle Termination
(An Asynchronous Synchronous Asynchronicity.)
The generation of the *DSACK1 signal from the Amiga *DTACK caused me
at times to doubt not only my own sanity but that of the universe
itself. The *DTACK signal from the Amiga should appear and be sampled
during the S4 phase of the clock cycle. Unfortunately it doesn't quite
know that. It responds more or less correctly when it is talking to
internal ram but when external (FAST) ram is accessed *DTACK comes
back almost right away. Remember that *DTACK is the only way we have
of determining the length of a cycle. We will cope with this anomaly
in a moment.
Since the 020 is operating at 16 MHz - i.e., quite asynchronous to the
Amiga clock - you have to sync up somewhere along the line with the
Amiga 7.16 MHz clock. The ideal place to do this is when the two Amiga
clocks C1 and C3 are in the condition C1 high and C3 low. These
signals are not available at the processor and for a long time I had
these two lines coming up off the motherboard. However the 7.16 MHz
clock that is available at the processor can produce a reasonable
facsimile. I divide the 7.16 MHz clock by two using U9a then logically
OR it with the original 7.16 MHz clock and this turns out to have the
same timing as C1 high and C3 low (my faith in the universe began to
rekindle at this point.)
In the PAL equations this is DTPRELIM (DTack PRELIMinary). Now we have
a reference point to sync back up with the Amiga.
In a saner world the combination of *DTACK and the Z1 signal (for
termination of VPA,VMA cycles) would be sufficient to create the term
SYSDSPRE1 (SYStem DSack1 PREliminary 1), but we have to delay till
*DTPRELIM is true to sync up with the Amiga, plus cope with the quick
responce of *DTACK anomaly when talking to fast ram. And sync back up
with the 16 MHz 68020 when we do finally issue a *DSACK1.
Confused? Wait! It gets better.
Most dynamic memory boards when connected to the Amiga expansion bus
will assert XRDY to hold off the assertion of *DTACK while they do a
refresh cycle. This puts in enough wait states so that the memory
board can complete a refresh cycle. Problem is, soon as XRDY is
asserted, a 20-30 ns. glitch occurs in *DTACK, prompting the 020 to
terminate the cycle before the data is even thinking about arriving on
the bus. The solution is to avoid decoding it till the S4 phase of the
Amiga 7.16 MHz clock. I delay *AS20DLY again for *DTQUAL and again for
*DTQUAL1. DTQUAL becomes part of the *DTACK term and *DTQUAL1 is wired
to QUAL (I needed the 7ns. across the PAL) then QUAL is added to the
*DTACK term, giving:
!SYSDSPRE1 = !Z1#
(!DTACK)&(!AS20DLY)&(!DTQUAL)&(!QUAL)
This soves the quick *DTACK problem.
We buffer this (another 7 ns.) by:
!BUFOUT = !SYSDSPRE1
Add in the Amiga syncronizing term
!DTTRIG = (!BUFOUT) & (!DTPRELIM)
Now we have an edge which is syncronous to the 7.16 MHz Amiga system.
We then use this to trigger a Flip-Flop which has patiently been
waiting for all this tom-foolery to end and will ship !SYSDACK1 to yet
another Flip-Flop to sync it back up to the 16 MHz 020 clock, and then
to the awaiting PAL U7 for additional decoding. I feed the Flip-Flop
U9b with *ASDLY so that the !SYSDSACK1 signal will terminate when *AS
does.
We're almost done.
PAL U7 then combines *SYSDSACK1 with the 68881 *DSACK1 , CPDSACK1, and
*SRDSACK1 (which comes from the expansion connector for future Static
Ram), and finally and enthusiastically begets *DSACK1.
What could be simpler?
*DSACK0 is generated from the 68881 and from the future Static Ram only.
Bus Arbitration
The Bus arbitration technique is quite similer to the 68000 with one
exception. During coprocessor cycles the *AS is blocked from the 68000
bus. This gives rise to a possible problem. If the 68020 begins a
coprocessor cycle with *AS blocked and responds to a alternate bus
master's *BR (Bus Request) with a *BG (Bus Grant) the 68020 will
assume the alternate bus master will wait for the negation of *AS.
Unfortunately *AS is blocked and therefore already negated. The result
is bus contention. Therefore we must prevent the assertion of *BG
until the interface negates *AS. This is done with the equation,
!BG00 = (!BG20) & (!Z2) & (AS20)
Benchmarks
To give some idea of the performance improvement you can expect with
the 68020-68881 pair, I have used 4 programs made available on the
DEVCON disks distributed at the Washington Developer's Conference.
Thanks to Al Aburto for letting me distribute them. These benchmarks
were run on an Amiga 1000 with a 2 Meg. Micrbotics Starboard memory
board and a Comspec 20 Meg. Hard Disk. The operating system was
Kickstart 1.2.1 and Workbench 1.3 Gamma 7. It should be noted that
when the 68020-68881 pair is installed the new IEEE math libraries
which support the 68881 are used for floating-point transparently. I
ran these benchmarks first with a standard 68000 and then with the
LUCAS board.
Savage:
68000 470.0 sec. Error -6.9e-7
LUCAS 14.5 sec. Error -5.7e-4
Whetstone:
68000 24 kwhets/sec.
LUCAS 126 kwhets/sec.
Calcpi:
68000 4.85 kflops/sec. Error -1.39e-11
LUCAS 11.9 kflops/sec. Error -2.78e-11
Float:
68000 10000 interations 45.74 sec.
256000 interations 286.96 sec.
LUCAS 10000 interations 12.80 sec.
256000 interations 118.56 sec.
Of course speed could be further enhanced by using inline F
instructions for the floating point stuff and even further enhanced by
using 32-bit wide no-wait-state Static Memory.
Please remember that benchmarks are like political speeches, they only
seem to make sense.
Software Considerations
Most software runs just fine on the 68020 but there are some programs
which will guru on you. One of the major reasons for this is that on
the 68020 all the instructions that are on the 68000 are implemented
with the inevitable exception of one: the MOVE SR <ea> instruction. On
the 68000 this is a user mode instruction; on the 68020 (and 68010 and
later parts) it is a supervisor mode only instruction, i.e., if its
executed on a 68020 in an Amiga you get a privelige violation guru. If
you're writing software, don't use this instruction; use instead the
GetCC() library function which translates to a MOVE CC <ea> on the
68020, which is a valid user mode instruction. This function
translates to a MOVE SR <ea> if there is a 68000 in the Amiga. This
way you're safe both ways.
If you're one of those people who thought encoding information in the
upper 8 bits of the address field was a nifty idea ... Oh well, time
to learn the error of your ways.
Of course if you use any instructions from the 68020 super set then
this code will never run on a standard Amiga. For further information
see section 21 of the Washington Amiga Developer Conference Notes,
"Software Issues in 32-bit Amiga Systems" by Dave Haynie.
The new release of 1.3 has new IEEE Double Precision Math Libraies
which take advantage of the 68020-68881 pair if it is present and can
immediately speed up any existing programs which use the math
libraries.
If you want blindingly fast floating point the best way is to
recompile your code so that it uses direct inline F instructions. I am
making available on the Transactor Disks two programs called Mandslow
and Mandfast. They are slight adaptations of RJ's original mandelbrot
program, adapted by Eric Haberfellner. These two programs are the same
except that mandslow was compiled for standard Amiga while mandfast
was compiled to use inline F instructions. As an example a moderately
deep mandelbrot which runs in 1 hr. 20 min. on a standard Amiga runs
in 4 min. 20 sec. with the LUCAS board installed.
Compatibility
The LUCAS board works with all the expansion boards I have but I'm
sure there will be some out there that will bomb out. I will keep a
list of those that do and those that don't and post it regularly on
Usenet and BIX. The ones I have are the Comspec 20 Meg. Hard Disk,
Comspec 2 Meg. Memory board, EASYL, and the Micobotics Starboard 2
Meg. Memory board.
As a matter of interest only, the board works fairly well at 20 MHz
but periodically bombs. I have only 16 MHz parts; when I debug the
bomb it seems to be the fault of the on-chip instruction cache. If you
have 20 MHz parts, try it and let me know. Even if you have 16 MHz
parts its worth the price of a 20 MHz crystal to see if it will work.
Who knows? You might get lucky.
Conclusion
The performance of the Amiga 1000 with the LUCAS board intalled will
be improved, but it won't perform miracles. For general purpose
computing I find that compiles are only about 1.4 times faster, hardly
worth the trouble. However, any program which uses Floating point will
be improved considerably, and those which have embedded F instructions
will indeed appear miraculous. On the other hand, the board does allow
for 32-bit wide expansion memory, and if installed you can expect
considerable general purpose performance improvements as well. I plan
to design two boards: one with standard 100 or 120 ns. DRAMs and a
second with some high speed Static Ram for no wait state operation at
16 MHz. You get most of the performance increase by having the memory
32 bits wide, but I can't resist seeing how fast it will go with no
wait states at 16 MHz.
Stay tuned to Transactor and the Nets for updates. Enjoy!
\Rogue\Monster\
else
echo "will not over write Transactor_Article"
fi
if [ `wc -c Transactor_Article | awk '{printf $1}'` -ne 21429 ]
then
echo `wc -c Transactor_Article | awk '{print "Got " $1 ", Expected " 21429}'`
fi
if `test ! -s Wiring_List`
then
echo "writing Wiring_List"
cat > Wiring_List << '\Rogue\Monster\'
%*********************************************************************
% *
% Program : PC-FORM VERSION 3.00 *
% Date : Jul 18 1988 *
% Time : 02:25:47 PM *
% File In : AM20AW27.PNL *
% File Out : AM20AW27.WRL *
% Format : WIRE LIST *
% *
%*********************************************************************
%
% NODE REF. DESIGNATOR-PIN
% ---- -------------------
%
D26 U2-60 U1-59
U3-17 DIN-88
D20 U2-17 U1-1
U3-53 DIN-79
D21 U2-62 U1-64
U3-20 DIN-81
D22 U2-16 U1-63
U3-19 DIN-82
D23 U2-99 U1-62
U3-51 DIN-84
D24 U2-61 U1-61
U3-18 DIN-85
D25 U2-15 U1-60
U3-49 DIN-87
A17 U2-110 U1-45
DIN-27 U4-7
D27 U2-98 U1-58
U3-16 DIN-90
D28 U2-14 U1-57
U3-48 DIN-91
AS00 U11-1 U11-2
U10-10
D30 U2-97 U1-55
U3-14 DIN-94
D31 U2-13 U1-54
U3-47 DIN-96
SIZE1 U2-54 DIN-37
U7-5
UN000025 U3-66 SIP1-3
SIZE0 U2-6 DIN-29
U7-4
RESET' U2-3 U1-18
U3-4 SIP1-6
A0 U2-114 DIN-1
U7-3
R/W00 R2-1 U11-9
A6 U2-36 U1-34
DIN-10
A7 U2-78 U1-35
DIN-12
A8 U2-37 U1-36
DIN-13
A9 U2-107 U1-37
DIN-15
A10 U2-79 U1-38
DIN-16
A11 U2-38 U1-39
DIN-18
A12 U2-108 U1-40
DIN-19
A13 U2-80 U1-41
DIN-21
A14 U2-39 U1-42
DIN-22
A15 U2-81 U1-43
DIN-24
A16 U2-109 U1-44
DIN-25 U4-8
UN002020 U9-2 U11-6
A18 U2-83 U1-46
DIN-28 U4-6
A19 U2-42 U1-47
DIN-30 U4-5
A20 U2-84 U1-48
DIN-31
UN001020 U1-9 R2-2
A22 U2-43 U1-51
DIN-34
A23 U2-44 U1-52
DIN-36
A3 U2-34 U1-31
U3-9 DIN-6
A1 U2-48 U1-29
U3-10 DIN-3
D3 U2-70 U3-33
DIN-54
D4 U2-26 U3-32
DIN-55
D5 U2-69 U3-61
DIN-57
D6 U2-68 U3-31
DIN-58
D7 U2-104 U3-30
DIN-60
D8 U2-24 U3-29
DIN-61
D9 U2-23 U3-68
DIN-63
D10 U2-67 U3-58
DIN-64
D11 U2-103 U3-27
DIN-66
D12 U2-22 U3-56
DIN-67
D13 U2-66 U3-57
DIN-69
D14 U2-21 U3-26
DIN-70
UN002004 U4-14 U5-7
D16 U2-64 U1-5
U3-23 DIN-73
D17 U2-18 U1-4
U3-54 DIN-75
D18 U2-63 U1-3
U3-22 DIN-76
D2 U2-27 U3-62
DIN-52
FC0 U2-5 U1-28
U4-4
FC1 U2-92 U1-27
U4-3
CPDSAK1' U3-13 SIP1-8
U7-15
UN001004 U3-6 SIP1-2
CPDSAK0' U3-46 SIP1-7
U7-8
AS20' U2-11 U3-8
SIP2-3 DIN-41
U5-18 U10-5
DSACK1' U2-9 U7-14
D19 U2-100 U1-2
U3-21 DIN-78
DSACK0' U2-94 U7-12
16M U2-50 U3-38
R1-2 R3-1
DIN-23 U6-1
U9-3 OSC-8
UN002018 U11-3 U10-12
UN000013 U2-8 SIP1-5
AVEC' U2-55 SIP1-4
J2-2
LDS' R6-1 U7-18
R/W20 U2-58 U3-11
DIN-53 U11-12
UN002012 U8-1 U8-2
U10-4
FC220 U2-53 U4-2
J1-1
BG20' U2-49 U5-9
DTACK' U1-10 U6-8
SRDSAK0' SIP1-10 DIN-65
U7-9
VPA' U1-21 U4-9
U5-2
IPL1' U2-29 U1-24
IPL2' U2-73 U1-23
HALT' U2-57 U1-17
BGACK' U2-1 U1-12
U5-8
BERR' U2-56 U1-22
DBEN' U2-93 DIN-59
UDS' R5-1 U7-19
VMA' U1-19 U5-17
U6-4
7M U1-15 U5-1
U6-5 U8-3
U8-11 U9-11
U11-11 U10-1
BR' U2-88 U1-13
BG00' U1-11 U5-19
E U1-20 U4-19
FC200 U1-26 J2-1
IPL0' U2-72 U1-25
AS00BUF' R4-1 U7-16
UN000021 U1-6 R4-2
UN000022 U1-7 R5-2
UN000023 U1-8 R6-2
A5 U2-35 U1-33
DIN-9
UN002011 U8-12 U8-13
U10-6
DS20' U2-12 U3-7
SIP2-4 DIN-47
U10-3
D15 U2-102 U3-25
DIN-72 OSC-11
A4 U2-77 U1-32
U3-42 DIN-7
OSC-6
D0 U2-28 U3-35
DIN-49
D1 U2-71 U3-34
DIN-51
DGND U2-2 U2-10
U2-19 U2-30
U2-40 U2-74
U2-75 U2-82
U2-95 U2-96
U2-101 U2-105
U1-16 U1-53
U3-3 U3-12
U3-24 U3-28
U3-36 U3-37
U3-39 U3-41
U3-50 U3-52
U3-60 U3-64
U3-65 R1-1
DIN-50 DIN-56
DIN-62 DIN-68
DIN-74 DIN-77
DIN-80 DIN-83
DIN-86 DIN-89
DIN-92 DIN-95
U4-10 U4-11
U5-10 U5-11
U6-10 U6-11
U8-7 U9-7
U11-7 U10-7
OSC-7 U7-10
C19-2 C7-2
C24-2 C28-2
C31-2 C15-2
C29-2 C5-2
C6-2 C32-2
C25-2 C30-2
C4-2 C13-2
C14-2 C12-2
C16-2 C2-2
C1-2 C27-2
C26-2 C23-2
C3-2 C33-2
C18-2 C22-2
C20-2 C21-2
C17-1 C11-1
C9-1 C8-1
C10-1
VCC U2-4 U2-20
U2-25 U2-31
U2-41 U2-51
U2-65 U2-90
U2-91 U2-106
U1-14 U1-49
U3-1 U3-2
U3-40 U3-44
U3-55 U3-59
U3-67 SIP1-1
SIP2-1 R3-2
DIN-2 DIN-5
DIN-8 DIN-11
DIN-14 DIN-17
DIN-20 DIN-26
DIN-32 DIN-38
DIN-43 DIN-44
U4-20 U5-20
U6-20 U8-4
U8-10 U8-14
U9-1 U9-4
U9-10 U9-13
U9-14 U11-4
U11-10 U11-13
U11-14 U10-14
OSC-14 U7-20
C19-1 C7-1
C24-1 C28-1
C31-1 C15-1
C29-1 C5-1
C6-1 C32-1
C25-1 C30-1
C4-1 C13-1
C14-1 C12-1
C16-1 C2-1
C1-1 C27-1
C26-1 C23-1
C3-1 C33-1
C18-1 C22-1
C20-1 C21-1
C17-2 C11-2
C9-2 C8-2
C10-2
A2 U2-76 U1-30
U3-43 DIN-4
7ME2 U6-7 U9-8
U9-12
DTTRIG' U6-18 U10-13
AS20DLY' U5-3 U6-2
U8-8 U7-6
Z3' U4-12 U6-3
UN000001 U4-17 U5-4
UN000002 U4-16 U5-5
UN000003 U4-15 U5-6
FC2 U4-13 J1-2
DS20DLY' U6-6 U8-6
U7-2
HIGHZ U5-13 U7-1
AS00' U5-12 U10-11
U7-17
QUAL' U6-9 U6-15
SYSDACK1 U9-5 U7-11
7M' U4-1 U10-2
CPCS' U3-45 U4-18
U7-7
SRDSAK1' SIP1-9 DIN-71
U7-13
D29 U2-59 U1-56
U3-15 DIN-93
A21 U2-111 U1-50
DIN-33
\Rogue\Monster\
else
echo "will not over write Wiring_List"
fi
if [ `wc -c Wiring_List | awk '{printf $1}'` -ne 16725 ]
then
echo `wc -c Wiring_List | awk '{print "Got " $1 ", Expected " 16725}'`
fi
echo "Finished archive 3 of 5"
# if you want to concatenate archives, remove anything after this line
exit
--
Bob Page, U of Lowell CS Dept. page@swan.ulowell.edu ulowell!page
Have five nice days.