page@swan.ulowell.edu (Bob Page) (02/04/89)
Submitted-by: cbmvax!daveh (Dave Haynie)
Posting-number: Volume 89, Issue 18
Archive-name: hardware/setcpu13.1
# This is a shell archive.
# Remove everything above and including the cut line.
# Then run the rest of the file through sh.
#----cut here-----cut here-----cut here-----cut here----#
#!/bin/sh
# shar: Shell Archiver
# Run the following text with /bin/sh to create:
# SetCPU.c
# 030Stuff.a
# makefile
# SetCPU.uu
# This archive created: Mon Jan 30 19:18:27 1989
cat << \SHAR_EOF > SetCPU.c
/*
SetCPU V1.3
by Dave Haynie (released to the public domain)
MAIN PROGRAM
This program tells which Motorola CPU is in place, and allows the
some cache control on 68020 and 68030 machines. It also sets up
the ExecBase->AttnFlags with 68030 information, so that any
subsequent program can use the standard methods to identify if the
system is a 68030 system.
The program now defaults to WALLOC mode for '030 data cache, since
that's the proper mode for Amiga data caches (user and supervisor
modes share data).
I now check for the existence of an MMU, and allow for testing of
different CPUs, for use in CLI scripts and that kind of thing.
Apparently some 68020 boards out there don't fully decode CPU space
addresses, and, as a result, their math chip shows up in all 8
coprocessor slots. This makes the MMU test hang, since instead of
getting no MMU, I get instead an FPU responding to an MMU
instruction, which will probably hang the system. The "NOMMUTEST"
option allows for the rest of this program to work on such a
board.
*/
#include <exec/types.h>
#include <exec/execbase.h>
#include <exec/nodes.h>
#include <exec/interrupts.h>
#include <functions.h>
#include <stdio.h>
/* Define a few flags missing from AmigaOS 1.2 */
#define AFB_68030 2L
#define AFF_68030 (1L<<2)
/* Define all CACR bit components, not all are actually used here. */
#define CACR_INST (1L<<0)
#define CACR_DATA (1L<<8)
#define CACR_WALLOC 5
#define CACR_BURST 4
#define CACR_CLEAR 3
#define CACR_ENTRY 2
#define CACR_FREEZE 1
#define CACR_ENABLE 0
/* ====================================================================== */
/* Some external declarations. */
void SetCACR();
ULONG GetCACR(), GetCPUType(), GetMMUType(), GetFPUType();
/* Checking array */
#define CK68000 0
#define CK68010 1
#define CK68020 2
#define CK68030 3
#define CK68851 4
#define CK68881 5
#define CK68882 6
#define CHECKS 7
struct checker { LONG item; BOOL tag; };
struct checker checks[CHECKS] = {
{ 68000L, FALSE },
{ 68010L, FALSE },
{ 68020L, FALSE },
{ 68030L, FALSE },
{ 68851L, FALSE },
{ 68881L, FALSE },
{ 68882L, FALSE }
};
USHORT code = 0L; /* Program return code */
/* ====================================================================== */
/* This replaces the Lattice "stricmp()" function, plus it's a better form
for my needs here. */
BOOL striequ(s1,s2)
char *s1,*s2;
{
while (*s1 && *s2 && (*s1++ & 0xdf) == (*s2++ & 0xdf));
return (BOOL) (!*s1 && (*s1 & 0xdf) == (*s2 & 0xdf));
}
/* This routine prints FPU codes and sets things accordingly. */
void PrintFPU(fpu)
ULONG fpu;
{
if (fpu == 68881L) {
printf("68881 ");
if (checks[CK68881].item) code = 0;
} else if (fpu == 68882L) {
printf("68882 ");
if (checks[CK68882].item) code = 0;
}
}
/* This be the main program. */
void main(argc,argv)
int argc;
char *argv[];
{
BOOL worked, dommutest = TRUE;
ULONG cacr,op,mode,test,cpu,fpu,mmu = 0;
USHORT i,j;
/* If they're just asking for help */
if (argc >= 2 && argv[1][0] == '?') {
printf("\2337mSetCPU 1.3 by Dave Haynie\2330m\n");
printf("Usage: SetCPU [INST|DATA] [[NO]CACHE|[NO]BURST] [NOMMUTEST]\n");
printf(" [CHECK 68000|68010|68020|68030|68851|68881|68882]\n");
exit(0);
}
/* Now we parse the command line. The default cache operation acts on
both data and instruction caches. The way all the cache control
functions are defined, they're just NOPs on machines without the
appropriate caches. */
mode = CACR_INST | CACR_DATA;
cacr = GetCACR();
if (argc > 1) {
for (i = 1; i < argc; ++i) {
if (striequ(argv[i],"CHECK")) {
code = 5;
while (argv[++i][0]=='6' && argv[i][1]=='8' && strlen(argv[i])==5) {
worked = FALSE;
sscanf(argv[i],"%ld",&test);
for (j = 0; j < CHECKS; ++j)
if (checks[j].item == test) {
checks[j].tag = TRUE;
worked = TRUE;
}
if (!worked) {
printf("Error: Illegal Check Parameter \"%s\"\n",argv[i]);
exit(10);
}
}
}
if (striequ(argv[i],"NOMMUTEST")) { dommutest = FALSE; ++i; }
if (striequ(argv[i],"DATA")) { mode = CACR_DATA; ++i; }
if (striequ(argv[i],"INST")) { mode = CACR_INST; ++i; }
if (striequ(argv[i],"CACHE") || striequ(argv[i],"NOCACHE"))
op = mode << CACR_ENABLE;
else if (striequ(argv[i],"BURST") || striequ(argv[i],"NOBURST"))
op = mode << CACR_BURST;
else {
if (argv[i][0] == 0) continue;
printf("Error: Illegal Cache Parameter \"%s\"\n",argv[i]);
exit(10);
}
argv[i][2] = '\0';
if (striequ(argv[i],"NO")) cacr &= ~op; else cacr |= op;
}
/* We ALWAYs want to be in Word Allocate mode, AmigaOS won't run
otherwise. */
SetCACR(cacr | CACR_DATA << CACR_WALLOC);
}
/* Let's find out what we have */
cpu = GetCPUType();
fpu = GetFPUType();
if (dommutest) mmu = GetMMUType();
printf("SYSTEM: ");
/* If they're not on a 68020/68030, we can't set anything. For
compatibility across systems, I don't consider a cache setting
request an error, just ignore it. */
if (cpu <= 68010L) {
if (cpu == 68010L) {
printf("68010 ");
if (checks[CK68010].item) code = 0;
} else {
printf("68000 ");
if (checks[CK68000].item) code = 0;
}
PrintFPU(fpu);
printf("\n");
exit(code);
}
/* Now we're on a 32 bit system. But EXEC doesn't know which. If you
run SetCPU on a 68030 system once, the '030 flag's set, otherwise,
we'll test for it. */
if (cpu == 68030L) {
printf("68030 ");
if (checks[CK68030].item) code = 0;
} else {
printf("68020 ");
if (checks[CK68020].item) code = 0;
}
PrintFPU(fpu);
if (mmu == 68851L) {
printf("68851 ");
if (checks[CK68851].item) code = 0;
}
/* We always print the results, even if nothing has changed. */
cacr = GetCACR();
printf("(INST: ");
if (!(cacr & (CACR_INST << CACR_ENABLE))) printf("NO");
printf("CACHE");
if (cpu == 68030L) {
printf(" ");
if (!(cacr & (CACR_INST << CACR_BURST))) printf("NO");
printf("BURST) (DATA: ");
if (!(cacr & (CACR_DATA << CACR_ENABLE)))
printf("NOCACHE ");
else
printf("CACHE ");
if (!(cacr & (CACR_DATA << CACR_BURST))) printf("NO");
printf("BURST");
}
printf(")\n");
/* For safety's sake, or personal paranoia, or whatever, I dump the
data cache before I go away. */
if (cpu = 68030L) SetCACR(cacr|(CACR_DATA << CACR_CLEAR));
exit(code);
}
SHAR_EOF
cat << \SHAR_EOF > 030Stuff.a
;======================================================================
;
; SetCPU V1.3
; by Dave Haynie (released to the public domain)
;
; 68030 Assembly Function Module
;
; This module contains functions that access the 68030 cache
; and run a few tests.
;
;======================================================================
;======================================================================
;
; Macros & constants used herein...
;
;======================================================================
CALLSYS macro *
jsr LVO\1(A6)
endm
CIB_ENABLE EQU 0
CIB_FREEZE EQU 1
CIB_ENTRY EQU 2
CIB_CLEAR EQU 3
CIB_BURST EQU 4
CDB_ENABLE EQU 8
CDB_FREEZE EQU 9
CDB_ENTRY EQU 10
CDB_CLEAR EQU 11
CDB_BURST EQU 12
CDB_WALLOC EQU 13
AFB_68030 EQU 2
ATNFLGS EQU $129
LVOSupervisor EQU -30
LVOFindTask EQU -294
LVOAllocTrap EQU -342
LVOFreeTrap EQU -348
;======================================================================
;
; Need just a little more stuff
;
;======================================================================
NOLIST
include "exec/execbase.i"
include "exec/tasks.i"
LIST
machine mc68020
mc68881
cseg
public _GetCACR
public _SetCACR
public _GetMMUType
public _GetCPUType
public _GetFPUType
;======================================================================
;
; This function returns the 68020/68030 CACR register. It assumes
; a 68020 or 68030 based system.
;
; ULONG GetCACR()
;
;======================================================================
_GetCACR:
move.l 4,a6 ; Get ExecBase
btst.b #AFB_68020,ATNFLGS(a6) ; Does the OS think an '020 is here?
bne 1$
moveq.l #0,d0 ; No CACR here, pal
rts
1$
move.l a5,-(sp) ; Save this register
lea 2$,a5 ; Get the start of the supervisor code
CALLSYS Supervisor
move.l (sp)+,a5 ; Give back registers
rts
2$
movec cacr,d0 ; Make CACR the return value
rte
;======================================================================
;
; This function sets the value of the 68020/68030 CACR register.
; It assumes a 68020 or 68030 based system.
;
; void SetCACR(cacr)
; ULONG cacr;
;
;======================================================================
_SetCACR:
move.l 4(sp),d0 ; New CACR is on stack
move.l 4,a6 ; Get ExecBase
btst.b #AFB_68020,ATNFLGS(a6) ; Does the OS think an '020 is here?
bne 1$
rts ; No CACR here, pal
1$
move.l a5,-(sp) ; Save this register
lea 2$,a5 ; Get the start of the supervisor code
CALLSYS Supervisor
move.l (sp)+,a5 ; Give back register
rts
2$
movec d0,cacr ; Set the CACR
rte
;======================================================================
;
; This function returns the type of the CPU in the system as a
; longword: 68000, 68010, 68020, or 68030. The testing must be done
; in reverse order, in that any higher CPU also has the bits set for
; a lower CPU. Also, since 1.3 doesn't recognize the 68030, if I
; find the 68020 bit set, I always check for the presence of a
; 68030.
;
; This routine should be the first test routine called under 1.2
; and 1.3.
;
; ULONG GetCPUType();
;
;======================================================================
_GetCPUType:
movem.l a4/a5,-(sp) ; Save this register
move.l 4,a6 ; Get ExecBase
btst.b #AFB_68030,ATNFLGS(a6) ; Does the OS think an '030 is here?
beq 0$
move.l #68030,d0 ; Sure does...
movem.l (sp)+,a4/a5
rts
0$
btst.b #AFB_68020,ATNFLGS(a6) ; Maybe a 68020
bne 2$
btst.b #AFB_68010,ATNFLGS(a6) ; Maybe a 68010?
bne 1$
move.l #68000,d0 ; Just a measley '000
movem.l (sp)+,a4/a5
rts
1$
move.l #68010,d0 ; Yup, we're an '010
movem.l (sp)+,a4/a5
rts
2$
move.l #68020,d0 ; Assume we're an '020
lea 3$,a5 ; Get the start of the supervisor code
CALLSYS Supervisor
movem.l (sp)+,a4/a5
rts
3$
movec cacr,d1 ; Get the cache register
move.l d1,a4 ; Save it for a minute
bset.l #CIB_BURST,d1 ; Set the inst burst bit
bclr.l #CIB_ENABLE,d1 ; Clear the inst cache bit
movec d1,cacr ; Try to set the CACR
movec cacr,d1
btst.l #CIB_BURST,d1 ; Do we have a set burst bit?
beq 4$
move.l #68030,d0 ; It's a 68030
bset.b #AFB_68030,ATNFLGS(a6)
4$
move.l a4,d1 ; Restore the original CACR
movec d1,cacr
rte
;======================================================================
;
; This function returns 0L if the system contains no MMU,
; 68851L if the system does contain an 68851, or 68030L if the
; system contains a 68030.
;
; This routine seems to lock up on at least some CSA 68020
; boards, though it runs just fine on those from Ronin and
; Commodore, as well as all 68030 boards it's been tested on.
;
; ULONG GetMMUType()
;
;======================================================================
_GetMMUType:
move.l 4,a6 ; Get ExecBase
movem.l a3/a4/a5,-(sp) ; Save this stuff
move.l #0,a1
CALLSYS FindTask ; Call FindTask(0L)
move.l d0,a3
move.l TC_TRAPCODE(a3),a4 ; Change the exception vector
move.l #2$,TC_TRAPCODE(a3)
subq.l #4,sp ; Let's try an MMU instruction
dc.w $f017 ; Slimey PMOVE tc,(sp)
dc.w $4200
cmpi #0,d0 ; Any MMU here?
beq 1$
btst.b #AFB_68030,ATNFLGS(a6) ; Does the OS think an '030 is here?
beq 1$
move.l #68030,d0
1$
addq.l #4,sp ; Return that local
move.l a4,TC_TRAPCODE(a3) ; Reset exception stuff
movem.l (sp)+,a3/a4/a5 ; and return the registers
rts
; This is the exception code. No matter what machine we're on,
; we get an exception. If the MMU's in place, we should get a
; privilige violation; if not, an F-Line emulation exception.
2$
move.l (sp)+,d0 ; Get Amiga supplied exception #
cmpi #11,d0 ; Is it an F-Line?
beq 3$ ; If so, go to the fail routine
move.l #68851,d0 ; We have MMU
addq.l #4,2(sp) ; Skip the MMU instruction
rte
3$
moveq.l #0,d0 ; It dinna woik,
addq.l #4,2(sp) ; Skip the MMU instruction
rte
;======================================================================
;
; This function returns the type of the FPU in the system as a
; longword: 0 (no FPU), 68881, or 68882.
;
; ULONG GetFPUType();
;
;======================================================================
_GetFPUType:
move.l a5,-(sp) ; Save this register
move.l 4,a6 ; Get ExecBase
btst.b #AFB_68881,ATNFLGS(a6) ; Does the OS think an FPU is here?
bne 1$
moveq.l #0,d0 ; No FPU here, dude
move.l (sp)+,a5 ; Give back the register
rts
1$
lea 2$,a5 ; Get the start of the supervisor code
CALLSYS Supervisor
move.l (sp)+,a5 ; Give back registers
rts
2$
move.l #68881,d0 ; Assume we're a 68881
fsave -(sp) ; Test and check
moveq.l #0,d1
move.b 1(sp),d1 ; Size of this frame
cmpi #$18,d1
beq 3$
move.l #68882,d0 ; It's a 68882
3$
frestore (sp)+ ; Restore the stack
rte
end
SHAR_EOF
cat << \SHAR_EOF > makefile
######################################################################
#
# Makefile for SetCPU V1.3
#
######################################################################
.a.o:
as -o $@ $*.a
CFLAGS = +x5
LFLAGS = -lc
OBJS = 030stuff.o setcpu.o
SetCPU: $(OBJS)
ln $(OBJS) -o SetCPU $(LFLAGS)
SHAR_EOF
cat << \SHAR_EOF > SetCPU.uu
begin 644 SetCPU
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size 8508
SHAR_EOF
# End of shell archive
exit 0
--
Bob Page, U of Lowell CS Dept. page@swan.ulowell.edu ulowell!page
Have five nice days.