page@swan.ulowell.edu (Bob Page) (03/16/89)
Submitted-by: cbmvax!daveh (Dave Haynie)
Posting-number: Volume 89, Issue 57
Archive-name: kernel/setcpu14.1
As well as fixing and extending the CHECK code, SetCPU V1.4 also has
some simple "FASTROM" code to allow 32 bit systems with MMUs to copy
ROM into RAM and then relocate this RAM as ROM, thus greatly enhancing
the speed of ROM based operations.
[uuencoded executables included. ..Bob]
# This is a shell archive.
# Remove everything above and including the cut line.
# Then run the rest of the file through sh.
#----cut here-----cut here-----cut here-----cut here----#
#!/bin/sh
# shar: Shell Archiver
# Run the following text with /bin/sh to create:
# SetCPU.txt
# ROMBash.c
# SetCPU.c
# 030Stuff.a
# makefile
# RomBash.uu
# SetCPU.uu
# This archive created: Wed Mar 15 13:44:12 1989
cat << \SHAR_EOF > SetCPU.txt
SetCPU V1.4
by Dave Haynie
(released to the public domain)
This program is designed to allow the user to detect and modify
various parameters related to 32 bit CPUs in Amiga computers. This program
began life as "WhatCPU", which did little more than read the proper place
in ExecBase and report what kind of CPU/FPU was in the system. The first
version of SetCPU added the capability to identify a 68030 and to change the
cache parameters of the 68020 and 68030 systems. The recently released SetCPU
V1.3 also did tests for 68882 vs. 68881, and for the presence of an MMU. It
was supposed to allow for checking of a particular thing in a startup
sequence, but unfortunately the CHECK code in V1.3 was broken.
That brings us up to V1.4. As well as fixing and extending the CHECK
code, SetCPU V1.4 also has some simple MMU code to allow 32 bit systems with
MMUs to copy ROM into RAM and then relocate this RAM as ROM, thus greatly
enhancing the speed of ROM based operations. This "FASTROM" code isn't
extremely sophisticated, and could possibly run into trouble on other 32 bit
systems, but it has been tested on the A2620. It will certainly have to be
rethought to work properly with memory outside of the 68000 compatible 24 bit
address space.
In any case, the syntax of the program is given as follows:
SetCPU [INST|DATA] [[NO]CACHE|[NO]BURST]
[[NO]FASTROM [TRAP]] [NOMMUTEST]
[CHECK 680x0|68851|6888x|MMU|FPU]
where "[]" indicates an optional parameter, "|" indicates a choice of
parameters. Typing "SetCPU ?" will retrieve this same syntax diagram.
Typing SetCPU alone will result in the SYSTEM configuration being
send to the console, my current system returns this:
SYSTEM: 68020 68881 68851 FASTROM (INST: CACHE)
This indicates I have a 68020/68881/68851 system (eg, standard A2620), I've
previously installed the FASTROM translation, and my instruction cache is
turned on (done by AmigaOS V1.2 or V1.3). Note that any parameters that
don't make sense to the real system configuration, such as asking to modify
the data cache on a 68020 system or install the FASTROM translation on a
68000 system are just ignored.
The individual commands are given below in detail:
[NO]CACHE
This command will switch on or off 68020 and 68030 caches. If
not qualified, it'll act on both instruction and data caches of
the 68030.
[NO]BURST
This command will switch on or off the burst cache line fill
request of the 68030. If not qualified, it'll act on both
instruction and data caches.
INST
This preceeds a CACHE or BURST operation to restrict it's application
to the instruction cache only.
DATA
This preceeds a CACHE or BURST operation to restrict it's application
to the data cache only.
[NO]FASTROM [TRAP]
This activates the FASTROM translation on or off an MMU equipped
system. When switching on, it first allocates 256K of memory for
the ROM image, then currenly 512 bytes of memory for the MMU table.
It copies the ROM into the image area, then applies the translation
by pointing the MMU at the table and activating it. The TRAP option
causes the MMU to look at all 32 bits of address; access to any
memory outside of the 24 bit space will result in an exception, which
if unhandled, results in a GURU 2. When TRAP is not specified, the
MMU is only looking at 24 bits of address space. This is the mode
you'd normally run in. Under V1.3 and earlier releases, a DOS bug
can cause invalid accesses, which cause the exception, when running
the EndCLI or NewCLI/NewShell programs; running untrapped will avoid
gurus with these commands. It's still possible to run into an
exception when running without the TRAP option. One easy way is
writing to the ROM image, which is write protected by the MMU. The
NOFASTROM option will switch off the MMU and reclaim the memory used
for the ROM image and MMU table. Note that this is achieved by
locating these items via the appropriate MMU registers. If any other
program set up the MMU for something, this could be a very bad thing
to do. In general, until there's some level of OS support for the
MMU in Amiga systems, you're really safe using only one MMU tool at
a time.
NOMMUTEST
This option won't normally be necessary. However, some 68020 boards
out there apparently have hardware bugs of some sort that make
testing for the MMU impossible, at least as near as I can tell. If
your 68020 board freezes, or crashes with some kind of coprocessor
protocol violation GURU (probably numbers $0D or $0E), you have a
problem with your 68020 board. The most common bug is the 68020
board hardware failing to fully decode CPU space, such that the FPU
in the system also responds to the MMU's address space.
CHECK
This option lets you check for the existence of a particular
CPU system component in a script. It works like this:
SetCPU CHECK 68020
If WARN
echo "No 68020 here!"
Else
echo "Sho nuff got a 68020 here!"
Endif
The arguments to CHECK can be any of:
68000 Matches the obvious
68010 "
68020 "
68030 "
68851 "
68881 "
68882 "
FPU Matches 68881 or 68882
MMU Matches 68851 or 68030
That's about it. As mentioned, this code is public domain, and you're
free to do anything with it you like. Even make it better! For any real
MMU programming, I'd recommend both "MC68030 Enhanced 32-Bit Microprocessor
User's Manual" and "MC68881 Paged Memory Management Unit User's Manual",
both from Motorola. There are some differences between the two, please make
sure, if you're writing any MMU code, that you either write code that works
on both, or you specifically check for each MMU and act accordingly.
Also note that much of what SetCPU does may be wrong in a future release of
the OS, so it's a very bad idea to put any of this stuff in a commercial
program. Things like identifying the MMU, CPU, or FPU that aren't fully
done in 1.3 may still work in a future OS release, but if that OS is
correctly identifying the MMU, CPU (eg, 68020 vs. 68030), or FPU (eg,
68881 vs. 68882), SetCPU should be using the OS's opinion of these items,
not testing itself. On a more drastic note, if an OS ever starts using
the MMU, the FASTROM code will certainly break. It's the job of the OS to
arbitrate the MMU, and if the OS is doing that, no legal program would be
able to come along and muck with the MMU registers without reeking havoc
on the operating system.
One final note, if you have a 68020 board that locks up without the
NOMMUTEST option, you'd be wise to express your concerns to the vendor
of that board. There's an awful good chance that if, in the future,
Amiga releases an operating system that knows about the MMU, it'll test
for it in some way, probably similar to what I do here. If your board
locks up on MMU operations, you may not be able to run this future OS
on your 68020 board. Maybe the vendors can fix these now, instead of
later when you really need this fixed.
-Dave Haynie
PLINK: D-Dave H
bix: hazy
usenet: {uunet,rutgers}!cbmvax!daveh
SHAR_EOF
cat << \SHAR_EOF > ROMBash.c
/* This program bashes on the ROM; basically, just copying the ROM around
several times. */
#include <exec/types.h>
#include <exec/nodes.h>
#include <exec/lists.h>
#include <exec/ports.h>
#include <exec/tasks.h>
#include <exec/devices.h>
#include <exec/io.h>
#include <devices/timer.h>
#include <libraries/dos.h>
struct Task *FindTask();
void SubTime(), *AllocMem();
struct Device *TimerBase;
/* This routine wastes time, based on ROM access. */
#define ROMBASE 0x00FC0000L
#define ROMSIZE 0x00030000L
void ROMBash() {
short ctr;
ULONG *mem;
mem = AllocMem(ROMSIZE,0L);
for (ctr = 0; ctr < 100; ++ctr) {
CopyMemQuick(ROMBASE,mem,ROMSIZE);
}
FreeMem(mem,ROMSIZE);
}
/* This is the main program. */
void main()
{
struct MsgPort port;
struct timerequest treq;
long pass;
struct timeval origtime, finaltime;
/* Initialize the timer stuff */
port.mp_Node.ln_Name = "ROMBash";
port.mp_Flags = PA_SIGNAL;
port.mp_SigTask = FindTask(0L);
port.mp_SigBit = AllocSignal(-1L);
AddPort(&port);
treq.tr_node.io_Message.mn_ReplyPort = &port;
if (OpenDevice(TIMERNAME,0L,&treq,0L) != 0) {
printf("Error: Can't get \"%s\"\n",TIMERNAME);
exit(20);
}
TimerBase = treq.tr_node.io_Device;
treq.tr_node.io_Command = TR_GETSYSTIME;
/* Find the starting time */
DoIO(&treq);
origtime = treq.tr_time;
ROMBash();
/* Find the ending time */
DoIO(&treq);
finaltime = treq.tr_time;
SubTime(&finaltime,&origtime);
printf("DONE: Elapsed time = %ld.%6ld seconds\n",
finaltime.tv_secs,finaltime.tv_micro);
CloseDevice(&treq);
RemPort(&port);
FreeSignal((ULONG)port.mp_SigBit);
}
SHAR_EOF
cat << \SHAR_EOF > SetCPU.c
/*
SetCPU V1.4
by Dave Haynie (released to the public domain)
MAIN PROGRAM
V1.4
I now add several commands in the assembly stub for manipulating
a few of the MMU registers. SetCPU now uses this to permit a
simple relocation of the ROM Kernel into 32 bit memory, which is
then translated back to the normal $00FC0000 base of the ROM
Kernel. This will increase system performance noticably.
V1.3
I now check for the existence of an MMU, and allow for testing of
different CPUs, for use in CLI scripts and that kind of thing.
Apparently some 68020 boards out there don't fully decode CPU space
addresses, and, as a result, their math chip shows up in all 8
coprocessor slots. This makes the MMU test hang, since instead of
getting no MMU, I get instead an FPU responding to an MMU
instruction, which will probably hang the system. The "NOMMUTEST"
option allows for the rest of this program to work on such a
board.
V1.2
The program now defaults to "WALLOC" mode for '030 data cache, since
that's the proper mode for Amiga data caches (user and supervisor
modes share data).
V1.1
This program tells which Motorola CPU is in place, and allows the
some cache control on 68020 and 68030 machines. It also sets up
the ExecBase->AttnFlags with 68030 information, so that any
subsequent program can use the standard methods to identify if the
system is a 68030 system.
*/
#define PROGRAM_VERSION "V1.4"
#include <exec/types.h>
#include <exec/execbase.h>
#include <exec/nodes.h>
#include <exec/interrupts.h>
#include <functions.h>
#include <stdio.h>
/* ====================================================================== */
/* Define all bit components used for manipulation of the Cache Control
Register. */
#define CACR_INST (1L<<0)
#define CACR_DATA (1L<<8)
#define CACR_WALLOC 5
#define CACR_BURST 4
#define CACR_CLEAR 3
#define CACR_ENTRY 2
#define CACR_FREEZE 1
#define CACR_ENABLE 0
/* ====================================================================== */
/* Define important bits used in various MMU registers. */
/* Here are the CRP definitions. The CRP register is 64 bits long, but
only the first 32 bits are control bits, the next 32 bits provide the
base address of the table. */
#define CRP_UPPER (1L<<31) /* Upper/lower limit mode */
#define CRP_LIMIT(x) ((ULONG)((x)&0x7fff)<<16)/* Upper/lower limit value */
#define CRP_SG (1L<<9) /* Indicates shared space */
#define CRP_DT_INVALID 0x00 /* Invalid root descriptor */
#define CRP_DT_PAGE 0x01 /* Fixed offset, auto-genned */
#define CRP_DT_V4BYTE 0x02 /* Short root descriptor */
#define CRP_DT_V8BYTE 0x03 /* Long root descriptor */
/* Here are the TC definitions. The TC register is 32 bits long. */
#define TC_ENB (1L<<31) /* Enable the MMU */
#define TC_SRE (1L<<25) /* For separate Supervisor */
#define TC_FCL (1L<<24) /* Use function codes? */
#define TC_PS(x) ((ULONG)((x)&0x0f)<<20) /* Page size */
#define TC_IS(x) ((ULONG)((x)&0x0f)<<16) /* Logical shift */
#define TC_TIA(x) ((ULONG)((x)&0x0f)<<12) /* Table indices */
#define TC_TIB(x) ((ULONG)((x)&0x0f)<<8)
#define TC_TIC(x) ((ULONG)((x)&0x0f)<<4)
#define TC_TID(x) ((ULONG)((x)&0x0f)<<0)
/* Here are the page descriptor definitions, for short desctriptors only,
since that's all I'm using at this point. */
#define PD_ADDR(x) ((ULONG)(x)&~0x0f) /* Translated Address */
#define PD_WP (1L<<2) /* Write protect it! */
#define PD_DT_INVALID 0x00 /* Invalid root descriptor */
#define PD_DT_PAGE 0x01 /* Fixed offset, auto-genned */
#define PD_DT_V4BYTE 0x02 /* Short root descriptor */
#define PD_DT_V8BYTE 0x03 /* Long root descriptor */
/* ====================================================================== */
/* Some external declarations. */
void SetCACR(), GetCRP(), SetCRP(), SetTC();
ULONG GetCACR(), GetTC(), GetCPUType(), GetMMUType(), GetFPUType();
/* Checking logic */
#define CK68000 0
#define CK68010 1
#define CK68020 2
#define CK68030 3
#define CK68851 4
#define CK68881 5
#define CK68882 6
#define CKFPU 7
#define CKMMU 8
#define CHECKS 9
#define WARNING 5
struct checker { char *item; BOOL tag; };
struct checker checks[CHECKS] = {
{ "68000", FALSE },
{ "68010", FALSE },
{ "68020", FALSE },
{ "68030", FALSE },
{ "68851", FALSE },
{ "68881", FALSE },
{ "68882", FALSE },
{ "FPU", FALSE },
{ "MMU", FALSE }
};
USHORT code = 0L; /* Program return code */
/* ====================================================================== */
/* This replaces the Lattice "stricmp()" function, plus it's a better form
for my needs here. */
static BOOL striequ(s1,s2)
char *s1,*s2;
{
BOOL aok;
while (*s1 && *s2 && (aok = (*s1++ & 0xdf) == (*s2++ & 0xdf)));
return (BOOL) (!*s1 && aok);
}
/* This routine prints FPU codes and sets things accordingly. */
static void PrintFPU(fpu)
ULONG fpu;
{
if (fpu == 68881L) {
printf("68881 ");
if (checks[CK68881].tag) code = 0;
} else if (fpu == 68882L) {
printf("68882 ");
if (checks[CK68882].tag) code = 0;
}
if (fpu && checks[CKFPU].tag) code = 0;
}
/* ====================================================================== */
/* Here's the MMU support stuff. */
#define ROUND 0x00001000L
#define ROMBASE 0x00FC0000L
#define ROMSIZE 0x00040000L
#define TABSIZE (128L * sizeof(ULONG))
/* Page tables and other MMU stuff must be on a page sized boundary, and
that boundary must be a power of two. This routine allocates such an
aligned block of memory. */
static void *AllocAligned(size,bound)
ULONG size;
ULONG bound;
{
void *mem, *aligned;
if (!(mem = AllocMem(size+bound,0L))) return NULL;
Forbid();
aligned = (void *)(((ULONG)mem + bound - 1) & ~(bound - 1));
FreeMem(mem,size+bound);
mem = AllocAbs(size,aligned);
Permit();
return mem;
}
/* This routine creates the Fast ROM. If the memory can't be allocated,
it returns FALSE, otherwise, TRUE. The "wrapbits" argument probably
won't work for every case. There's some magic here which I seem to
have working, but don't understand completely. Basically, the TC
register must be correct, or you'll get a configuration exception,
otherwise know as GURU #38. The big constraint is that sum of the
TIx fields from A to the first zero field, plus PS and IS, must be
equal to 32. */
static BOOL CreateFastROM(wrapbits)
short wrapbits;
{
ULONG i, myCRP[2], myTC, *ROM32 = NULL, *MMUTable = NULL;
/* First off, get the memory for the 32 bit ROM and the MMU table. */
ROM32 = AllocAligned(ROMSIZE,ROUND);
MMUTable = AllocAligned(TABSIZE,ROUND);
if (!ROM32 || !MMUTable) {
if (MMUTable) FreeMem(MMUTable,TABSIZE);
if (ROM32) FreeMem(ROM32,ROMSIZE);
return FALSE;
}
/* Here I set up the ROM, as quickly as possible! */
CopyMemQuick(ROMBASE,ROM32,ROMSIZE);
/* Now I initialize the MMU table. This translation is really very
basic. I set up one table level and use direct page translation
on a grain of 128K per entry. Everything's directly mapped except
for the last two entries, which is for the $FC0000-$FFFFFF area.
This I translate to my fastram ROM, and write protect it too. */
for (i = 0; i < 126; i++) MMUTable[i] = PD_ADDR(i<<17)|PD_DT_PAGE;
MMUTable[126] = PD_ADDR(ROM32)|PD_WP|PD_DT_PAGE;
MMUTable[127] = PD_ADDR(((ULONG)ROM32)+0x20000L)|PD_WP|PD_DT_PAGE;
/* Now I have to set up the MMU. The CPU Root Pointer tells the MMU about
the table I've set up, and the Translation Control register will turn
the thing on. Note that the first half of the CRP is control data, the
second the address of my table. */
myCRP[0] = CRP_LIMIT(0x007f)|CRP_SG|CRP_DT_V4BYTE;
myCRP[1] = (ULONG)MMUTable;
SetCRP(myCRP);
myTC = TC_ENB|TC_PS(0x0c)|TC_IS(wrapbits)|
TC_TIA(0x0f-wrapbits)|TC_TIB(0x05)|TC_TIC(0)|TC_TID(0);
SetTC(myTC);
return TRUE;
}
/* This routine remover the Fast ROM, and re-claims the memory previously
allocated. We've already checked to make sure that the MMU was
switched on. */
static void DeleteFastROM() {
ULONG myCRP[2], *ROM32 = NULL, *MMUTable = NULL;
/* First off, turn of the MMU. This lets us muck with the table and
reclaim memory without any trouble. */
SetTC(0L);
/* Now get the root pointer, which will tell where the memory has been
allocated. */
GetCRP(myCRP);
MMUTable = (ULONG *)myCRP[1];
ROM32 = (ULONG *)PD_ADDR(MMUTable[126]);
/* Now I just free up the memory, and I'm done! */
FreeMem(MMUTable,TABSIZE);
FreeMem(ROM32,ROMSIZE);
}
/* ====================================================================== */
/* Codes for the FASTROM action. */
#define FR_NO_ACTION 0
#define FR_CREATE 1
#define FR_DELETE 2
/* This be the main program. */
int main(argc,argv)
int argc;
char *argv[];
{
BOOL worked, dommutest = TRUE, fastrom = FR_NO_ACTION;
ULONG cacr,op,mode,test,cpu,fpu,mmu = 0;
USHORT i,j;
short wrapbits = 8;
/* If they're just asking for help */
if (argc >= 2 && argv[1][0] == '?') {
printf("\2337mSetCPU %s by Dave Haynie\2330m\n",PROGRAM_VERSION);
printf("Usage: SetCPU [INST|DATA] [[NO]CACHE|[NO]BURST]\n");
printf(" [[NO]FASTROM [TRAP]] [NOMMUTEST]\n");
printf(" [CHECK 680x0|68851|6888x|MMU|FPU]\n");
exit(0);
}
/* Now we parse the command line. The default cache operation acts on
both data and instruction caches. The way all the cache control
functions are defined, they're just NOPs on machines without the
appropriate caches. */
mode = CACR_INST | CACR_DATA;
cacr = GetCACR();
if (argc > 1) {
for (i = 1; i < argc; ++i) {
if (code == WARNING) for (j = 0; j < CHECKS; ++j)
if (striequ(checks[j].item,argv[i])) {
checks[j].tag = TRUE;
break;
}
if (striequ(argv[i],"CHECK")) code = WARNING;
else if (striequ(argv[i],"FASTROM")) fastrom = FR_CREATE;
else if (striequ(argv[i],"NOFASTROM")) fastrom = FR_DELETE;
else if (striequ(argv[i],"TRAP")) wrapbits = 0;
else if (striequ(argv[i],"NOMMUTEST")) dommutest = FALSE;
else if (striequ(argv[i],"DATA")) mode = CACR_DATA;
else if (striequ(argv[i],"INST")) mode = CACR_INST;
else if (striequ(argv[i],"CACHE")) cacr |= mode << CACR_ENABLE;
else if (striequ(argv[i],"NOCACHE")) cacr &= ~(mode << CACR_ENABLE);
else if (striequ(argv[i],"BURST")) cacr |= mode << CACR_BURST;
else if (striequ(argv[i],"NOBURST")) cacr &= ~(mode << CACR_BURST);
}
/* We ALWAYs want to be in Word Allocate mode, AmigaOS won't run
otherwise. */
SetCACR(cacr | CACR_DATA << CACR_WALLOC);
}
/* Let's find out what we have, and perform the ROM translation, if it's
requested and hasn't been done already. */
cpu = GetCPUType();
fpu = GetFPUType();
if (dommutest && (mmu = GetMMUType())) {
if (!(GetTC() & TC_ENB)) {
if (fastrom == FR_CREATE && !CreateFastROM(wrapbits)) {
printf("Error: Can't get memory for FASTROM translation\n");
exit(10);
}
} else if (fastrom == FR_DELETE)
DeleteFastROM();
}
printf("SYSTEM: ");
/* If they're not on a 68020/68030, we can't set anything. For
compatibility across systems, I don't consider a cache setting
request an error, just ignore it. */
if (cpu <= 68010L) {
if (cpu == 68010L) {
printf("68010 ");
if (checks[CK68010].tag) code = 0;
} else {
printf("68000 ");
if (checks[CK68000].tag) code = 0;
}
PrintFPU(fpu);
printf("\n");
exit(code);
}
/* Now we're on a 32 bit system. But EXEC doesn't know which. If you
run SetCPU on a 68030 system once, the '030 flag's set, otherwise,
we'll test for it. */
if (cpu == 68030L) {
printf("68030 ");
if (checks[CK68030].tag) code = 0;
} else {
printf("68020 ");
if (checks[CK68020].tag) code = 0;
}
PrintFPU(fpu);
if (mmu == 68851L) {
printf("68851 ");
if (checks[CK68851].tag) code = 0;
}
if (mmu && checks[CKMMU].tag) code = 0;
if (mmu && (GetTC() & TC_ENB)) printf("FASTROM ");
/* We always print the results, even if nothing has changed. */
cacr = GetCACR();
printf("(INST: ");
if (!(cacr & (CACR_INST << CACR_ENABLE))) printf("NO");
printf("CACHE");
if (cpu == 68030L) {
printf(" ");
if (!(cacr & (CACR_INST << CACR_BURST))) printf("NO");
printf("BURST) (DATA: ");
if (!(cacr & (CACR_DATA << CACR_ENABLE)))
printf("NOCACHE ");
else
printf("CACHE ");
if (!(cacr & (CACR_DATA << CACR_BURST))) printf("NO");
printf("BURST");
}
printf(")\n");
/* For safety's sake, or personal paranoia, or whatever, I dump the
data cache before I go away. */
if (cpu = 68030L) SetCACR(cacr|(CACR_DATA << CACR_CLEAR));
exit(code);
}
SHAR_EOF
cat << \SHAR_EOF > 030Stuff.a
;======================================================================
;
; SetCPU V1.4
; by Dave Haynie (released to the public domain)
;
; 68030 Assembly Function Module
;
; This module contains functions that access functions in the 68020,
; 68030, and 68851 chips, and ID all of these, plus the 68881/68882
; FPU chips.
;
;======================================================================
;======================================================================
;
; Macros & constants used herein...
;
;======================================================================
CALLSYS macro *
jsr LVO\1(A6)
endm
CIB_ENABLE EQU 0
CIB_FREEZE EQU 1
CIB_ENTRY EQU 2
CIB_CLEAR EQU 3
CIB_BURST EQU 4
CDB_ENABLE EQU 8
CDB_FREEZE EQU 9
CDB_ENTRY EQU 10
CDB_CLEAR EQU 11
CDB_BURST EQU 12
CDB_WALLOC EQU 13
AFB_68030 EQU 2
ATNFLGS EQU $129
LVOSupervisor EQU -30
LVOFindTask EQU -294
LVOAllocTrap EQU -342
LVOFreeTrap EQU -348
;======================================================================
;
; Need just a little more stuff
;
;======================================================================
NOLIST
include "exec/execbase.i"
include "exec/tasks.i"
LIST
machine mc68020
mc68881
cseg
;**********************************************************************
;
; This section contains functions that identify and operate on CPU
; things.
;
;**********************************************************************
public _GetCPUType ; ID the CPU
public _GetCACR ; Get 020/030 CACR register
public _SetCACR ; Set 020/030 CACR register
;======================================================================
;
; This function returns the type of the CPU in the system as a
; longword: 68000, 68010, 68020, or 68030. The testing must be done
; in reverse order, in that any higher CPU also has the bits set for
; a lower CPU. Also, since 1.3 doesn't recognize the 68030, if I
; find the 68020 bit set, I always check for the presence of a
; 68030.
;
; This routine should be the first test routine called under 1.2
; and 1.3.
;
; ULONG GetCPUType();
;
;======================================================================
_GetCPUType:
movem.l a4/a5,-(sp) ; Save this register
move.l 4,a6 ; Get ExecBase
btst.b #AFB_68030,ATNFLGS(a6) ; Does the OS think an '030 is here?
beq 0$
move.l #68030,d0 ; Sure does...
movem.l (sp)+,a4/a5
rts
0$
btst.b #AFB_68020,ATNFLGS(a6) ; Maybe a 68020
bne 2$
btst.b #AFB_68010,ATNFLGS(a6) ; Maybe a 68010?
bne 1$
move.l #68000,d0 ; Just a measley '000
movem.l (sp)+,a4/a5
rts
1$
move.l #68010,d0 ; Yup, we're an '010
movem.l (sp)+,a4/a5
rts
2$
move.l #68020,d0 ; Assume we're an '020
lea 3$,a5 ; Get the start of the supervisor code
CALLSYS Supervisor
movem.l (sp)+,a4/a5
rts
3$
movec cacr,d1 ; Get the cache register
move.l d1,a4 ; Save it for a minute
bset.l #CIB_BURST,d1 ; Set the inst burst bit
bclr.l #CIB_ENABLE,d1 ; Clear the inst cache bit
movec d1,cacr ; Try to set the CACR
movec cacr,d1
btst.l #CIB_BURST,d1 ; Do we have a set burst bit?
beq 4$
move.l #68030,d0 ; It's a 68030
bset.b #AFB_68030,ATNFLGS(a6)
4$
move.l a4,d1 ; Restore the original CACR
movec d1,cacr
rte
;======================================================================
;
; This function returns the 68020/68030 CACR register. It assumes
; a 68020 or 68030 based system.
;
; ULONG GetCACR()
;
;======================================================================
_GetCACR:
move.l 4,a6 ; Get ExecBase
btst.b #AFB_68020,ATNFLGS(a6) ; Does the OS think an '020 is here?
bne 1$
moveq.l #0,d0 ; No CACR here, pal
rts
1$
move.l a5,-(sp) ; Save this register
lea 2$,a5 ; Get the start of the supervisor code
CALLSYS Supervisor
move.l (sp)+,a5 ; Give back registers
rts
2$
movec cacr,d0 ; Make CACR the return value
rte
;======================================================================
;
; This function sets the value of the 68020/68030 CACR register.
; It assumes a 68020 or 68030 based system.
;
; void SetCACR(cacr)
; ULONG cacr;
;
;======================================================================
_SetCACR:
move.l 4(sp),d0 ; New CACR is on stack
move.l 4,a6 ; Get ExecBase
btst.b #AFB_68020,ATNFLGS(a6) ; Does the OS think an '020 is here?
bne 1$
rts ; No CACR here, pal
1$
move.l a5,-(sp) ; Save this register
lea 2$,a5 ; Get the start of the supervisor code
CALLSYS Supervisor
move.l (sp)+,a5 ; Give back register
rts
2$
movec d0,cacr ; Set the CACR
rte
;**********************************************************************
;
; This section contains functions that identify and operate on
; MMU things. Unfortunately, there aren't any MMU op-codes in
; the Manx assembler yet, so I have to fudge them here.
;
;**********************************************************************
public _GetMMUType ; Returns the type of MMU
public _GetCRP ; Gets MMU CRP register
public _SetCRP ; Sets MMU CRP register
public _GetTC ; Gets MMU TC register
public _SetTC ; Gets MMU TC register
;======================================================================
;
; This function returns 0L if the system contains no MMU,
; 68851L if the system does contain an 68851, or 68030L if the
; system contains a 68030.
;
; This routine seems to lock up on at least some CSA 68020
; boards, though it runs just fine on those from Ronin and
; Commodore, as well as all 68030 boards it's been tested on.
;
; ULONG GetMMUType()
;
;======================================================================
_GetMMUType:
move.l 4,a6 ; Get ExecBase
movem.l a3/a4/a5,-(sp) ; Save this stuff
move.l #0,a1
CALLSYS FindTask ; Call FindTask(0L)
move.l d0,a3
move.l TC_TRAPCODE(a3),a4 ; Change the exception vector
move.l #2$,TC_TRAPCODE(a3)
subq.l #4,sp ; Let's try an MMU instruction
dc.w $f017 ; Slimey PMOVE tc,(sp)
dc.w $4200
cmpi #0,d0 ; Any MMU here?
beq 1$
btst.b #AFB_68030,ATNFLGS(a6) ; Does the OS think an '030 is here?
beq 1$
move.l #68030,d0
1$
addq.l #4,sp ; Return that local
move.l a4,TC_TRAPCODE(a3) ; Reset exception stuff
movem.l (sp)+,a3/a4/a5 ; and return the registers
rts
; This is the exception code. No matter what machine we're on,
; we get an exception. If the MMU's in place, we should get a
; privilige violation; if not, an F-Line emulation exception.
2$
move.l (sp)+,d0 ; Get Amiga supplied exception #
cmpi #11,d0 ; Is it an F-Line?
beq 3$ ; If so, go to the fail routine
move.l #68851,d0 ; We have MMU
addq.l #4,2(sp) ; Skip the MMU instruction
rte
3$
moveq.l #0,d0 ; It dinna woik,
addq.l #4,2(sp) ; Skip the MMU instruction
rte
;======================================================================
;
; This function returns the MMU CRP register. It assumes a 68020
; system with MMU, or a 68030 based system (eg, test for MMU before
; you call this, or you wind up in The Guru Zone). Note that the
; CRP register is two longwords long.
;
; void GetCRP(ULONG *)
;
;======================================================================
_GetCRP:
move.l 4(sp),a0 ; Pointer to the CRP storage area
move.l 4,a6 ; Get ExecBase
move.l a5,-(sp)
lea 2$,a5 ; Get the start of the supervisor code
CALLSYS Supervisor
move.l (sp)+,a5
rts
2$
dc.w $f010 ; PMOVE CRP,(a0)
dc.w $4e00
rte
;======================================================================
;
; This function sets the MMU CRP register. It assumes a 68020
; system with MMU, or a 68030 based system (eg, test for MMU before
; you call this, or you wind up in The Guru Zone). Note that the
; CRP register is two longwords long.
;
; void SetCRP(ULONG *)
;
;======================================================================
_SetCRP:
move.l 4(sp),a0 ; Pointer to the CRP storage area
move.l 4,a6 ; Get ExecBase
move.l a5,-(sp)
lea 2$,a5 ; Get the start of the supervisor code
CALLSYS Supervisor
move.l (sp)+,a5 ; Give back registers
rts
2$
dc.w $f010 ; PMOVE (a0),CRP
dc.w $4c00
rte
;======================================================================
;
; This function returns the MMU TC register. It assumes a 68020
; system with MMU, or a 68030 based system (eg, test for MMU before
; you call this, or you wind up in The Guru Zone).
;
; ULONG GetTC()
;
;======================================================================
_GetTC:
move.l 4,a6 ; Get ExecBase
move.l a5,-(sp)
subq.l #4,sp ; Make a place to dump TC
move.l sp,a0
lea 2$,a5 ; Get the start of the supervisor code
CALLSYS Supervisor
move.l (sp),d0 ; Here's the result
addq.l #4,sp
move.l (sp)+,a5
rts
2$
dc.w $f010 ; PMOVE TC,(a0)
dc.w $4200
rte
;======================================================================
;
; This function sets the MMU TC register. It assumes a 68020
; system with MMU, or a 68030 based system (eg, test for MMU before
; you call this, or you wind up in The Guru Zone).
;
; void SetTC(ULONG)
;
;======================================================================
_SetTC:
lea 4(sp),a0 ; Get address of our new TC value
move.l 4,a6 ; Get ExecBase
move.l a5,-(sp)
lea 2$,a5 ; Get the start of the supervisor code
CALLSYS Supervisor
move.l (sp)+,a5
rts
2$
dc.w $f010 ; PMOVE (a0),TC
dc.w $4000
rte
;**********************************************************************
;
; This section contains functions that identify and operate on
; FPU things.
;
;**********************************************************************
public _GetFPUType ; Gets the FPU type
;======================================================================
;
; This function returns the type of the FPU in the system as a
; longword: 0 (no FPU), 68881, or 68882.
;
; ULONG GetFPUType();
;
;======================================================================
_GetFPUType:
move.l a5,-(sp) ; Save this register
move.l 4,a6 ; Get ExecBase
btst.b #AFB_68881,ATNFLGS(a6) ; Does the OS think an FPU is here?
bne 1$
moveq.l #0,d0 ; No FPU here, dude
move.l (sp)+,a5 ; Give back the register
rts
1$
lea 2$,a5 ; Get the start of the supervisor code
CALLSYS Supervisor
move.l (sp)+,a5 ; Give back registers
rts
2$
move.l #68881,d0 ; Assume we're a 68881
fsave -(sp) ; Test and check
moveq.l #0,d1
move.b 1(sp),d1 ; Size of this frame
cmpi #$18,d1
beq 3$
move.l #68882,d0 ; It's a 68882
3$
frestore (sp)+ ; Restore the stack
rte
end
SHAR_EOF
cat << \SHAR_EOF > makefile
######################################################################
#
# Makefile for SetCPU V1.3
#
######################################################################
.a.o:
as -o $@ $*.a
CFLAGS = +x5
LFLAGS = -lc
OBJS = 030stuff.o setcpu.o
SetCPU: $(OBJS)
ln $(OBJS) -o SetCPU $(LFLAGS)
ROMBash: ROMBash.o
ln $*.o -o ROMBash $(LFLAGS)
SHAR_EOF
cat << \SHAR_EOF > RomBash.uu
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end
size 8004
SHAR_EOF
# End of shell archive
exit 0
--
Bob Page, U of Lowell CS Dept. page@swan.ulowell.edu ulowell!page
Have five nice days.