hjs@LINDY.STANFORD.EDU (Harry Saal) (11/02/88)
Drawing conclusions about the relative capabilities of the Intel 82586 vs. Lance based on two different controller subsystem designs doesn't truly indicate the limits or lack thereof in these chips. Whether the 82586 is able to keep up with high traffic rates depends on the surrounding hardware design (to minimize bus latency and wait states) and on the driver software; there is nothing inherent in the design of the chip itself that prevents indefinite reception of back-to-back packets. We do it in the Sniffer (at least in highspeed mode), but it does require a fair degree of heroics and a careful reading of the latest bugsheet from Intel; some modes will generate "dma overrun" regardless of how fast the memory bus is. On the transmit side, though, we have not been able to generate back-to-back packets; the minimum interframe spacing that a single 82586 can manage seems to be about 40 usec instead of 9.6. For us that's no big deal since we're just trying to generate traffic to load the network, and 1500-byte packets separated by 40 usec is about 97% of maximum rate anyway. It might be true (and this is speculation as to what might have resulted in the measurements reported by Van) that designing a high performance controller and writing the drivers is a tougher job for the 82586 than for the Lance. However this is something you do just once, so there is no excuse not to squeeze the most out of the chip's capabilities.