Alessandro.Forin@SPICE.CS.CMU.EDU (08/18/90)
Hi all, after painful efforts I tracked down a problem in my ethernet driver (for Mach/DECStations). It would look like the Amd7990 loses the content of the CSR1 register, which the spec say it would not (not even across RESET). I have looked at CSR1 and found it had the wrong content after 1) the chip reports a MISS packet 2) I send STOP to CSR0 3) I perform the INIT sequence (e.g. INIT, wait for done) 4) I restart the chip Since the chip was stuck at this point, I conjecture CSR1 was wrong already at point 3). Resetting the CSR1 value and restarting from 3) got it working again. I have looked at my code over and over again, and I can find no way in which the value that I see in the register (0x48) could have got there intentionally. Indeed, the RAP register is not ever touched after power up time ! And the machine was fully functional and continued to work after I dropped into the kernel debugger and fixed the registers by hand. Sooo, can anyone confirm the chip can violate the requirement that CSR1 stays set ? Or deny it ? [Might also depend on the revisions: my pmax is one of the first ones, and the problem does not show up (yet?) on a newer machine.] Pointers&illuminations are most welcome. Incidentally, I have another horror story for the same chip, would anyone at AMD care to hear it ? sandro- Alessandro Forin / School of Computer Science / Carnegie-Mellon University Schenley Park / Pittsburgh, PA 15213 / Ph: (412) 268-6861 ARPA: af@cs.cmu.edu
Alessandro.Forin@SPICE.CS.CMU.EDU (08/20/90)
The AMD people sent me a mail that cleared up the air: there is a little note in the spec of the effects of the STOP bit that states explicitly "CSR1, CSR2 and CSR3 must be reloaded when the STOP bit is set". Needless to say, I had not noticed [lesson: always read on to the next page!!]. Apologies to AMD for the rumoring, and BTW I am finding them most responsive and cooperative. Thanks! sandro-