mwang@watmath.UUCP (mwang) (11/23/83)
_U_N_I_V_E_R_S_I_T_Y _O_F _W_A_T_E_R_L_O_O _D_E_P_A_R_T_M_E_N_T _O_F _C_O_M_P_U_T_E_R _S_C_I_E_N_C_E _j_o_i_n_t_l_y _w_i_t_h _D_E_P_A_R_T_M_E_N_T _O_F _E_L_E_C_T_R_I_C_A_L _E_N_G_I_N_E_E_R_I_N_G PRESENTS A COMPUTER ARCHITECTURE SEMINAR ON Real Time Debuggers with P. Parkinson Department of Electrical Engineering University of Waterloo DATE: Monday, November 28, 1983 at 3:30 PM ROOM: MC 6091A ABSTRACT The debugging of real time systems with control complexes consisting of many processors is a rather difficult task. One of the most severe failures in such systems are proces- sor crashes. Available instrumentation does not satisfac- torily support the debugging of infrequent crashes that only occur in some field locations. The design of an intelligent bus tracer which builds up a record of correct processor behavior and triggers when it sees a deviationn from this behavior is presented. The tracer relies on a common fault-tolerance mechanism (watchdog timer) to draw conclu- sions about correct program behavior and exploits a fine structuring of the processor address space. Although origi- nally developed for peripheral processors in large telecom- munications switching machines, it could be used in any oth- er high availability systems with man-machine interfaces, suitable processors, and program execution patterns. November 23, 1983