mwang@watmath.UUCP (mwang) (01/17/84)
_D_E_P_A_R_T_M_E_N_T _O_F _C_O_M_P_U_T_E_R _S_C_I_E_N_C_E
_U_N_I_V_E_R_S_I_T_Y _O_F _W_A_T_E_R_L_O_O
_S_E_M_I_N_A_R _A_C_T_I_V_I_T_I_E_S
_V_L_S_I _S_E_M_I_N_A_R
- Thursday, January 26, 1984.
Prof. S. Przybylski of Stanford University will speak
on ``The MIPS Processor: Motivation and Architecture.''
TIME: 10:30 AM (Talk I)
ROOM: E2-3324 (Please Note)
ABSTRACT
The MIPS microprocessor is a high performance, 32-bit
machine designed and implemented at Stanford University
over the last three years. Born of the risc philoso-
phy, its low-level streamlined instruction set is
tailored to the execution of compiled code. The most
notable architectural features are pipeline interlocks
implemented as a code generation postpass, word ad-
dressed split instruction and data streams, the sophis-
ticated system support, the elimination of condition
codes and the two level definition of the instruction
set. This first of two seminars deals with the motiva-
tion behind Reduced Instruction Set Computers, and the
details of the MIPS architecture. The software system
that forms a key part of the architecture and its im-
plementation will also be discussed. The many interac-
tions between the architecture, organization and VLSI
implementation will be illustrated under the general
heading of hardware/software tradeoffs.
Coffee will be provided.
January 17, 1984