[ont.events] UW VLSI Seminar, Prof. Przybylski on "The MIPS Processor: Implementation and Testing"

mwang@watmath.UUCP (mwang) (01/17/84)

_D_E_P_A_R_T_M_E_N_T _O_F _C_O_M_P_U_T_E_R _S_C_I_E_N_C_E
_U_N_I_V_E_R_S_I_T_Y _O_F _W_A_T_E_R_L_O_O
_S_E_M_I_N_A_R _A_C_T_I_V_I_T_I_E_S

_V_L_S_I _S_E_M_I_N_A_R
                           - Thursday, January 26, 1984.

Prof. S. Przybylski of Stanford University  will  speak
on ``The MIPS Processor: Implementation and Testing.''

TIME:                3:30 PM (Talk II)

ROOM:              MC 5158

ABSTRACT

The MIPS microprocessor is a high  performance,  32-bit
machine designed and implemented at Stanford University
over the last three years.  This second of two seminars
will  concentrate on the VLSI implementation of the ar-
chitecture described in the first talk.  The  resulting
circuit contains 25,000 transistors and occupies 5mm by
6mm at 3um feature sizes.  At the projected speed of  a
250ns  machine cycle time, the part out performs a 8MHz
M68000 by a factor of 5.  Including  the  architectural
and  the compiler efforts, the project took 7 man years
to complete.  The presentation will concentrate on  the
methodology  used in the electrical and physical design
and the CAD tools available.  The  strong  interactions
between the architecture and its implementation will be
viewed from the  hardware  perspective.   Finally,  the
trials and tribulations of debugging and testing a com-
plex microprocessor will be discussed, along with  pro-
posed  directions  in  computer aided design.  The MIPS
microprocessor is a high  performance,  32-bit  machine
designed  and  implemented  at Stanford University over
the last three years.  Born of the risc philosophy, its
low-level  streamlined  instruction  set is tailored to
the execution of compiled code.  The most  notable  ar-
chitectural features are pipeline interlocks implement-
ed as a code generation postpass, word addressed  split
instruction  and data streams, the sophisticated system
support, the elimination of condition codes and the two
level definition of the instruction set.  This first of
two seminars deals with the motivation  behind  Reduced
Instruction  Set Computers, and the details of the MIPS
architecture.  The software system  that  forms  a  key
part  of  the  architecture and its implementation will
also be discussed.  The many interactions  between  the
architecture, organization and VLSI implementation will
be   illustrated   under   the   general   heading   of
hardware/software tradeoffs.

                   January 17, 1984

                         - 2 -

Coffee will be provided at 3:00 PM.

                   January 17, 1984