[comp.compilers] What is a scoreboard?

johnl@ima.ISC.COM (12/14/87)

Can someone explain the technique of using "scoreboards" in 
compiler development?  Any references?
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meissner@mcnc.org (12/18/87)

In article <797@ima.ISC.COM>, ...!harvard!talcott!motcoh!mark writes:
> Can someone explain the technique of using "scoreboards" in 
> compiler development?  Any references?

    I don't have any hard references, but when I ran into the CDC 6600
hardware it was described as having a hardware scoreboard.  With regard
to compilers, it comes up with some of the RISC designs, where the
compiler has to do instruction scheduling and branch delays.  I would
imagine that is where the term came from.

    A scoreboard keeps track of the various functional units of the
machine, and will not allow access to a unit, until it finishes.  For
example, if divide takes 8 clock units, a scoreboard would indicate that
the any reference within the 8 clock units to either the input and
result registers would pend instructions.  Even if the hardware provides
such a scoreboard, on such machines it is usually an advantage to have
the compiler know about these delays, so that it can try to do more
stuff in parallel.
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Michael Meissner, Data General.		Uucp: ...!mcnc!rti!xyzzy!meissner
					Arpa/Csnet:  meissner@dg-rtp.DG.COM
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wallach@seismo.CSS.GOV (12/24/87)

/* Written  9:00 am  Dec 18, 1987 by johnl@ima.UUCP in convex:comp.compilers */
In article <797@ima.ISC.COM>, ...!harvard!talcott!motcoh!mark writes:
> Can someone explain the technique of using "scoreboards" in 
> compiler development?  Any references?

    I don't have any hard references, but when I ran into the CDC 6600
hardware it was described as having a hardware scoreboard.  With regard
to compilers, it comes up with some of the RISC designs, where the
compiler has to do instruction scheduling and branch delays.  I would
imagine that is where the term came from.

    A scoreboard keeps track of the various functional units of the
machine, and will not allow access to a unit, until it finishes.  For
example, if divide takes 8 clock units, a scoreboard would indicate that
the any reference within the 8 clock units to either the input and
result registers would pend instructions.  Even if the hardware provides
such a scoreboard, on such machines it is usually an advantage to have
the compiler know about these delays, so that it can try to do more
stuff in parallel.
--
Michael Meissner, Data General.		Uucp: ...!mcnc!rti!xyzzy!meissner
					Arpa/Csnet:  meissner@dg-rtp.DG.COM
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/* End of text from convex:comp.compilers */

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johnl@ima.UUCP (12/25/87)

In article <808@ima.ISC.COM> xyzzy!meissner@mcnc.org writes:
|In article <797@ima.ISC.COM>, ...!harvard!talcott!motcoh!mark writes:
|> Can someone explain the technique of using "scoreboards" in 
|> compiler development?  Any references?
|
|    I don't have any hard references, but when I ran into the CDC 6600
|hardware it was described as having a hardware scoreboard. 

  It could also be a misnomer for a "register history", which is
useful on machines without any visible parallellization, to keep
track of what register currently holds what variable or value.  For
an example, see:
  Jim Welsh and Michael McKag, "Structures Systems Programming",
Englewood Cliffs, N.J. (Prentice-Hall), 1980.

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