norvell@csri.toronto.edu (Theodore Stevens Norvell) (12/16/88)
I am interested in references on compilers for decoupled architectures and
machines with a similar register structure (such as the CDC 170 and the Crays).
A decoupled CPU consists of two or more processors which each read the
instruction stream at their own rate. Typically there is one
processor for address calculation and another for other calculations.
The idea is that the address calculation processor will typically be
farther ahead in the instruction stream, than the other processors
and so can request loads well in advance of the time the data is needed
by the other processors. The processors communicate with each other and
with the memory interface only through fifo queues.
In order to minimize communication from the integer calculation processor
to the address calculation unit (such communication forces the address
processor to stop until the integer processor has caught up and is hence
undesirable), the register set is split into (at least) index registers,
which reside in the address processor, and data registers which reside
in the other processors. This in much like the 170 with its B (index)
and X (data) registers, and the Cray with its B (index) and, S and T (data)
registers. This presents an interesting register allocation problem.
E.g. Given a loop
for( i = 0 ; i < N ; ++i ) {
A[i] = B[i] + z ;
}
It is best to allocate i and N index registers and A[i], B[i], and z to
data registers. To make matters worse, the width of the index registers
may be less than the width of data registers so that they may not hold
an entire C int or Fortran integer.
Any pointers to literature discussing this sort of problem would be
greatly appreciated, as would comments from people who have looked
at this sort of problem.
norvell@csri.toronto.edu
or {utzoo, decvax, ...}!utcsri!norvell
Theo Norvell
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mail accidentally sent back to compilers. Meta-mail to ima!compilers-requestseanf@uunet.uu.net (Sean Fagan) (12/21/88)
In article <3058@ima.ima.isc.com> Theodore Stevens Norvell <norvell@csri.toronto.edu> writes: >I am interested in references on compilers for decoupled architectures and >machines with a similar register structure (such as the CDC 170 and the Crays). [my favorite word 8-)] [brief description of splitting of registers given] Well, I worked on a Cyber 170 for quite a while, and looked a bit into what GCC would need to get it to work (you've always wanted 60-bit char's right?). Basicly, there isn't a big problem for compiler written for that machine. FTN5, for the Cyber, would put index registers and DO loop variables into the 18-bit B registers (unless you told it you wanted "big" DO loops, in which case it used a 60-bit X register). Making gcc work, on the other hand, would not do such a thing (because a B register is a register of class Pointer, for which it has at least some basic hooks), unless the person describing the cyber to gcc were really clever (which I'm not 8-)). Also, in your example, if N is a constant, and less than 2**17, than it would be best to put it into an index register. A[i], B[i], and z should go into data registers, as you said. However, on a Cray, you could probably vectorize it, splitting it up (at run time?) to do it in chunks of 64 A's and B's. -- Sean Eric Fagan | "Merry Christmas, drive carefully and have some great sex." seanf@sco.UUCP | -- Art Hoppe (408) 458-1422 | Any opinions expressed are my own, not my employers'. -- Send compilers articles to ima!compilers or, in a pinch, to Levine@YALE.EDU Plausible paths are { decvax | harvard | yale | bbn}!ima Please send responses to the originator of the message -- I cannot forward mail accidentally sent back to compilers. Meta-mail to ima!compilers-request