Chuck_Lins.SIAC_QMAIL@gateway.qm.apple.com (Chuck Lins) (02/21/91)
In a previous posting and subject, Michael Orr asks about retargeting GCC to
an unusual machine type. I'd like to raise the question about machine
descriptions in general. It seems from all the papers I've read on this topic
that the research has focused on the VAX-11, MC680x0, PDP-11, IBM 360/370
kind of architecture. I don't remember much being done with SPARC, MIPS,
HP-PA RISC, 88000, ARM, architectures. Everybody ignores floating-point (and
fp coprocessors). And almost no one addresses run-time environments (I
remember one paper but I forget the author).
It seems that we're a very long way from a truely general machine description
mechanism. So long as you remain in the 'normal' and 'standard' kinds of
architectures machine description is ok; otherwise you have to build your
back-end the "old-fashioned" way - by hand. (IMHO you can still take
advantage of newer compiler technology, it's just not automated. You might
even have to find your own peephole optimizations.)
Is this an accurate assessment? If not, I'm sure someone will happily point
out the gaps in my knowledge (which I know to be significant :-)
--
Send compilers articles to compilers@iecc.cambridge.ma.us or
{ima | spdcc | world}!iecc!compilers. Meta-mail to compilers-request.dgb@cs.washington.edu (David Bradlee) (02/22/91)
In article <9102201924.AA14610@internal.apple.com>, Chuck_Lins.SIAC_QMAIL@gateway.qm.apple.com (Chuck Lins) writes: > It seems from all the papers I've read on this topic that the research has > focused on the VAX-11, MC680x0, PDP-11, IBM 360/370 kind of architecture. I > don't remember much being done with SPARC, MIPS, HP-PA RISC, 88000, ARM, > architectures. Yes, most previous work was on CISCs. But recently, Robert Henry, Susan Eggers and I have worked on retargetable instruction scheduling for RISCs. We build back ends that include instruction selection, register allocation and instruction scheduling from a machine description. The description is more like the Fraser/Davidson model than the Graham/Glanville. A paper on the system will appear in this year's SIGPLAN'91 PLDI conference (June). David Bernstein and Michael Rodeh will also have a paper there that talks about their system for scheduling across basic block boundaries. > It seems that we're a very long way from a truely general machine > description mechanism. Nothing is truly general. Our description can cover a lot of RISCs but some features are hard. It's a start. I think we'll see a lot more on instruction scheduling in the next few years. Dave Bradlee Department of Computer Science and Engineering, FR-35 University of Washington Seattle, WA 98195 206-543-7798 (dgb@cs.washington.edu) -- Send compilers articles to compilers@iecc.cambridge.ma.us or {ima | spdcc | world}!iecc!compilers. Meta-mail to compilers-request.