[comp.compilers] Instruction Scheduling

rajeevc@mipos2.intel.com (06/27/89)

I am looking for good articles , references on code ordering / Instruction
scheduling . Any pointers would be appreciated...

Thanks

Rajeev Chandrasekhar
Intel Corp            >> theres someone in my head, and its not me << 
2625, Walsh Ave MS SC4-59                      (408) 765-4632
Santa Clara, CA 95051  {hplabs,oliveb}!intelca!mipos2!rajeevc                      
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bron@bronze.wpd.sgi.com (Bron Campbell Nelson) (07/06/89)

Rajeev Chandrasekhar of Intel asked for articles on Instruction Scheduling.
I thought there might be some general interest in the topic, so thought
I'd send my list to comp.compilers.  These are papers I've found interesting,
along with my own biased comments.


	Thomas Gross, "Code Optimization of Pipeline Constraints",
	technical report #83-255, dec 1983
	Computer Systems Lab, EECS, Stanford University, Stanford CA.
	(or his PhD thesis which is more or less the same; I don't
	have the reference).
	This is the technology that MIPSco instruction re-ordering
	is (or at least was originally) based on.

	Gibbons and Muchnick, "Efficient Instruction Scheduling for
	a Pipelined Architecture", SIGPLAN Compiler Construction
	proceedings, 1986.
	The HP Precision Architecture.  Strongly based on Gross's work.

	J.R. Ellis, "Bulldog: A Compiler for VLIW Architechtures," PhD
	thesis, Yale University.  Also published by MIT press as part
	of the ACM Doctoral Disertation Award Series.
	The definitive work on trace scheduling.  Used by Multiflow.


	Rajiv Gupta and Mary Lou Soffa, "Region Scheduling"  Proceedings
	of the 2nd International Conf. on Supercomputing, 1987.
	Refinements on the idea of trace scheduling.  The paper descibes
	work in progress, not demonstrated technology, but it looks to
	have promise.

	Wei-Chung Hsu, "Register Allocation and Code Scheduling for Load/Store
	Architectures", PhD thesis, University of Wisconsin - Madison,
	1987.
	A good integration of earlier works.  Tries to deal with the
	interdependency of register allocation and code scheduling.


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Bron Campbell Nelson
bron@sgi.com  or possibly  ..!ames!sgi!bron
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budd@bu-it.BU.EDU (Phil Budne) (07/11/89)

Several years ago I did the scheduler for a doomed CISC to RISC
translator (while working for a vendor which has only recently entered
the RISC market).

Here are some (dated) papers; Where I'm not sure of the Journals for I
have included the reprint IDs;

J.A. Fisher "Trace Scheduling: A Technique for Global Microcode
Compaction" IEEE Transactions on Computers, Volume C-30, No. 7, pp.
478-490, July 1981

A. Nicolau, J.A. Fisher "Using an Orale to Measure Potential
Parallelism in Single Stream Programs" 094-1895/81/0000/0171 $00.75
(c)1981 IEEE

J.L. Linn "SRDAG Compaction - A Generalization of Trace Scheduling to
Increase the use of Global Context Information" (c) 1983 ACM
0-89791-114/8/83/0010/0011 $00.75

J. Lah, D.E. Atkins "Tree Compaction of Microprograms" (c) 1983 ACM
0-89791-114/8/83/0010/0023 $00.75

J.A. Fisher, J.R. Ellis, ... "Parallel Processing: A Smart Compiler
and a Dumb Machine" Proceedings of the '84 Symposium on Compiler
Construction, SIGPLAN Notices v19, n6, June 1984

D. Bernstein, R.Y. Pinter, ... "Optimal Scheduling of Arithmetic
Operations in Parallel with Memory Access" (c) 1984 ACM
0-89791-147-4/85/001/0325 $00.75

J.A. Fisher "The VLIW Machine: A Multiprocessor for Compiling
Scientific Code" IEEE Computer, July 1984
[From budd@bu-it.BU.EDU (Phil Budne)]
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horst@techfak.uni-bielefeld.de (Horst Hogenkamp) (06/11/91)

I am very interested in instruction scheduling.
Which books, articles etc. (published or unpublished) do you know of?

Depending on the number of answers, I will post or mail a summary.

Thank you
Horst Hogenkamp <horst@techfak.uni-bielefeld.de>
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