giebelhaus@hi-csc.UUCP (Timothy R. Giebelhaus) (03/10/88)
I went to a talk by the product manager for the Apollo DN10000. Here is
a summary of what I heard.
The machine is a multi-processor machine. Apollo will license the
architecture. Apollo has made most of the hardware themselves.
The speed of the machine should be 15-30 times the speed of the
vax 11/780 for one processor and 60-100 times faster for four
processors. The machine has a high speed bus, high speed ECC memory,
and 15 meg / sec throughput on their disks. The following bench
marks were quoted: Drystone: 27,000 and 5 Linpack Mflops (64 bit).
The machine is also supposed to do 30,000 to 40,000 vector operations
per second.
The cost is a base of $69,900 for a DSP node with one CPU, 8 meg memory,
and a 348 disk. A screen costs $10,00 and extra cpus costs $20,000 each.
The machine is a 64 bit machine. Disk striping is supported.
The CPU is a single cycle machine except for three operations:
floating point divide, integer divide, and square root. That is, one
instruction can start each cycle, although it may take more than a
cycle for an instruction to finish. The CPU is a RISC cpu, though it seems
a large reduced instruction set to me. The computer can do two floating point
vector operations in a cycle (such as multiply and then add). The hardware
also includes clipping and transformation functions for graphics.
There has been lots of diagnostics build into the machine. There is a bus,
a Motorola 68020, and 15% of the gate arrays dedicated to running diagnostics.
They use "scan path technology" which isolates any failures to the chip level.
There are two booklets full of information if you want more info.
Disclaimer: I don't promise all my notes were complete or correct. I hope
this helps the people in comp.sys.apollo who wanted more info about the Dn10000,
though.
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Nobody I know admits to sharing my opinions. I don't even have a pet
which will share my opinion.adam@hyper.lap.upenn.edu (Adam Feigin) (03/11/88)
There's an article highlighting the DN10000 in the March 3,1988 issue of
Electronics entitled: "Surprise! Apollo unveils a 'desktop' supercomputer"
(pages 69-70)....
Some excerpts:
"...among other things, the PRISM (Parallel RIS Microprocessor) design makes
the 10000 the first RISC system to hit an execution rate of more than 1
instruction per cycle...executes 1.2 to 1.3 instructions per cycle....first
workstation to with a true 64-bit system architecture, including CPU, FPU, and
system buses....."
"...A fast -- 150,000 Mbyte/sec CMOS system bus called the X bus links the CPU,
memory, and graphics subsystems"
Oh yes, the article goes on to mention that the graphics subsystem won't be
available until a few months after the base systems ship, due to the fact that
the design was started after the CPU design.
I suppose we'll all have to wait until an 'official' product announcement
makes it here for more concrete details !!! (Are you listening Apollo ??? :-})
Adam
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Adam Feigin
Network Administrator
Language Analysis Project
University of Pennsylvania
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