young-jonathan@YALE.ARPA (Jonathan Young) (03/15/88)
I have a copy of "The Series 10000 Personal Supercomputer",
a glossy release from Apollo about their new archictecture.
I have pulled out some of the key phrases, which appear below.
--- Jonathan
Features:
RISC CPUs
single-cycle LOAD/STOREs
fixed-length instructions
delayed branches
up to 3 operations in parellel
(1 fp mpy, 1 fp, 1 integer)
IP and FPU
Multiprocessor Design
up to 4 CPUs
Fast System Bus
150 megabyte/sec
64 bit data paths
Shared Virtual Memory
High-speed IP
Multistaged pipeline (variable depth)
Power Shifter (32 bits)
32x32 register file
Low-latency, High-performance FP
in parallel with IP
ALU and multiplier (also in parallel)
64x32 or 32x64 register file
multiported (1Gbyte/sec)
Cache
Dedicated 128K byte instruction cache, 64 bits wide
64K byte data cache, 64 bits wide
virtually indexed
physically tagged
validation across processors
write-through
Multiprocessor Cache Coherency
Compilers
Data flow scheduling
High Bandwidth Main Memory
100ns static CMOS DRAMs
modules are 8 or 16Mbyte
Read Multiple
32 bit ECC: single error correction,
double error detection
Disk striping
Graphics
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