ylfink@water.UUCP (ylfink) (10/15/86)
DEPARTMENT OF COMPUTER SCIENCE
UNIVERSITY OF WATERLOO
SEMINAR ACTIVITIES
VLSI SEMINAR
- Thursday, October 16, 1986.
Dr. Douglas Reeves of Pennsylvania State will speak on
``Functional Verification of Digital MOS Circuits''.
TIME: 3:30 PM
ROOM: MC 5158
ABSTRACT
A major task in implementing a VLSI circuit is
determining whether the design is correct. This is
usually done by testing extensively with a suite of CAD
tools, including switch-level simulators. By contrast,
my approach is an attempt to prove that a design is
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correct at the switch-level. This is done in two steps:
1) the function computed by the circuit is determined
by analyzing the layout, and 2) this function is then
compared to a high-level specification of the intended
function.
My contributions are primarily in three areas.
First, optimized algorithms for analyzing the circuit
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are presented which improve on the performance of pre-
viously published methods by more than an order of mag-
nitude. Secondly, static analysis of the circuit is
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performed to eliminate repetitive work during sequen-
tial verification. Thirdly, hierarchy and replication
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are exploited to make verification of large designs
feasible.
These ideas have been implemented in the program V,
and tested on a variety of circuits to demonstrate
their validity. This software is part of the SNAP sys-
tem, developed at Pennsylvania State University, for
automatically designing and validating VLSI circuits
for high-performance signal processing tasks.
October 15, 1986