cfry@watdcsu.waterloo.edu (C.Fry - Inst. Computer Research) (02/17/88)
Interconnection Networks for Multiprocessors
by
Prof. Carl Hamacher
of
Departments of Electrical Engineering
and Computer Science,
and the Computer Systems Research Institute
University of Toronto
Abstract
Multistage Interconnection Networks (MINs) have been proposed for
many years as high-performance networks for parallel, processor-
to-memory interconnections in tightly-coupled multiprocessor sys-
tems. However, they have only recently begun to appear in real
systems of significant size; and then, only in research proto-
types. This talk will present some performance aspects of vari-
ous MINs over the range of network sizes (64 to 1024
processory/memory pairs) that is appearing in these systems.
Some generalizations of the basic MIN switch will also be ex-
plored briefly, in order to suggest a possible area for future
research in computer communications.
DATE: February 24, 1988
TIME: 3:30 p.m.
PLACE: MC 5158
Everyone is welcome. Refreshments served.