clarke@csri.toronto.edu (Jim Clarke) (08/23/88)
(SF = Sandford Fleming Building, 10 King's College Road) SUMMARY: THEORY SEMINAR, Wednesday, August 24 at 11 a.m., SF1101 -- Noam Nisan: "Multiparty Protocols and Logspace-Hard Pseudorandom Sequences" SYSTEMS SEMINAR, Thursday, August 25, 11 am, SF1101 -- Garth Gibson: "Symbolic Processing Using RISCs: SPUR A Retrospective on the Cache Controller Development." ----------------------------- THEORY SEMINAR, Wednesday, August 24 at 11 a.m., SF1101 Noam Nisan U. California, Berkeley "Multiparty Protocols and Logspace-Hard Pseudorandom Sequences" We construct a pseudo-random sequence generator that "stretches" a short seed of truly random bits to a long string which "looks random" to any Logspace Turing machine. Unlike the known con- structions of pseudo- random generators which require some unpro- ven "hardness" assumption, we make no unproven assumptions but rather reduce the problem to that of proving lower bounds on the complexity of the following multiparty communi- cation game: Let f(x1,x2,...,xk) be a Boolean function that k parties wish to colla- boratively evaluate. The i'th party knows each input argu- ment except xi; and each party has unlimited computational power. They share a blackboard, viewed by all parties, where they can exchange messages. The objective is to minimize the number of bits written on the board. We prove lower bounds for the number of bits that need to be ex- changed, by that completing the proof of the security of the pseudo-random gen- erator. SYSTEMS SEMINAR, Thursday, August 25, 11 am, SF1101 Garth Gibson Univ. of California at Berkeley "Symbolic Processing Using RISCs: SPUR A Retrospective on the Cache Controller Development." SPUR is a multifaceted Berkeley project that is building a loosely coupled network of high-performance, shared-memory multiprocessors with hardware support for LISP and cache coherency. Each processor is composed of a 128KB cache and three custom CMOS chips: a CPU, a floating point coprocessor, and a cache controller. Advanced features of the cache controller chip are in-cache address translation and hardware cache coherency. In this talk I will introduce the architecture of SPUR and describe some of our experiences with complete system building in a university. I will focus on the project stages of specification, simulation, testing, and sys- tem integration by following the development of the cache controller. -- Jim Clarke -- Dept. of Computer Science, Univ. of Toronto, Canada M5S 1A4 (416) 978-4058 BITNET,CSNET: clarke@csri.toronto.edu CDNNET: clarke@csri.toronto.cdn UUCP: {allegra,cornell,decvax,linus,utzoo}!utcsri!clarke