pc@eecg.toronto.edu (Paul Chow) (10/26/88)
Dr. John G. Shaw Xerox Palo Alto Research Center 3333 Coyote Hill Road Palo Alto, CA 94025 will speak on Two-Dimensional Simulations of Current Flow in Amorphous Silicon TFTs Friday, October 28, 1988 1:00 - 2:00 p.m. Room 202, Galbraith Building University of Toronto ABSTRACT Recent advances in large-area electronics have lead to several new classes of amorphous silicon thin-film transis- tors (a-Si:H TFTs). Typical applications of this technology include: flat-panel displays, full-width printer arrays, and electro-optical sensing bars. These devices are built by depositing and etching thin layers of dielectric and amorphous silicon on a large insulating substrate. In order to fully understand their operation, it is desirable to model and analyze a-Si:H TFTs using a numerical device simu- lator such as MANIFEST. Unlike single crystal devices, the behaviour of a-Si:H transistors is largely governed by the large concentration of trapped charge induced by defects in the semiconductor. This charge must be fully accounted for by any simulator and requires a detailed density-of-states (DOS) model in the semiconductor's band-gap. Simulations of three modern a-Si:H devices will be shown: a conventional TFT; a high-voltage TFT; and a new "vertical" transistor for high-current applications.