[ont.events] Formal Specification and Modeling of Self-Timed Queue Circuits.

ylfink@water.waterloo.edu (ylfink) (11/01/88)

DEPARTMENT OF COMPUTER SCIENCE
UNIVERSITY OF WATERLOO
SEMINAR ACTIVITIES

ASYNCHRONOUS CIRCUITS SEMINAR

                    -  Thursday, November 3, 1988

Dr.  David  Dill, Stanford University, California, will
speak  on  ``Formal Specification and Modeling of Self-
Timed Queue Circuits''.

TIME:                3:00 PM  PLEASE NOTE TIME

ROOM:              DC 1304

ABSTRACT

By  considering  self-timed  queue  circuits,  we  will
highlight  theoretical  and  practical  issues  in  the
formal  modeling,  specification,  and  verification of
speed-independent     circuits.      The     user-level
specifications are petri nets, which are given a deeper
semantics  based  on sets of sequences (called traces).
The  examples  can  be  worked automatically.  Both the
advantages  and  limitations  of  our  approach will be
discussed.

This  is  joint  work  with  Robert  Sproull and Steven
Nowick.