tomg@chance.mitre.org (Tom Gerasch) (02/01/91)
I need some information about instruction cacheing on the Symmetry.
I have been told that the 128KB cache that each processor has on
the Symmetry is used only for data, that instructions are not cached.
I would think that the movement of instructions over the bus when one
has a medium to large Symmetry configuration would tend to saturate
the bus. I know that the Intel 386 processor has a 16 byte on-chip
instruction queue, but some simple back-of-the-envelope calculations
seem to indicate that with 16 processors, say, and assuming that the
instructions executed are 2 to 4 bytes long and take 4 to 8 clocks, on
the average (I know, not real arithmetic computation), that we would
be getting near 50% utilization of the available bus bandwidth just
moving instructions around. Am I wrong in this?
If anyone can provide me with information and/or analytic models with
reasonable instruction mix assumptions, I would appreciate it. If the
caches hold instructions as well as data, is there any way for the
programmer to control the percentage of cache allocated for each?
I would also appreciate any information on how Sequent makes use of the
Intel code and data segment descriptors. Do they just create a single,
huge segment for each? Do they share the same segment?
Any information will be appreciated.
Thanks,
Tom Gerasch MITRE-Washington Software Engineering Center
tomg@mitre.org
--
Dr. Tom Gerasch, Lead Scientist DDN: tgerasch@mitre.org
MITRE-Washington C3 Division tomg@mitre.org
Software Engineering Center
7525 Colshire Drive (703) 883-7895 jjb@sequent.UUCP (Jeff Berkowitz) (02/02/91)
In article <1991Feb1.153112.14717@linus.mitre.org> tomg@chance.mitre.org (Tom Gerasch) writes: >I have been told that the 128KB cache that each processor has on >the Symmetry is used only for data, that instructions are not cached. This is incorrect. The cache does not know one part of the *process* address space from another. All references to memory during normal system execution (*) are made "through" the cache. (*) Standalone diagnostic software, etc, can disable the cache for test purposes. >I would think that the movement of instructions over the bus when one >has a medium to large Symmetry configuration would tend to saturate >the bus. Perhaps this would be a problem if in fact instructions were not cached. However, they are. >If the caches hold instructions as well as data, is there any way for >the programmer to control the percentage of cache allocated for each? No, because it is a physical cache. That is, each physical address in main memory maps to particular location (actually two, because the cache is two-way-set-associative) in the cache; this is not under programmer control. >I would also appreciate any information on how Sequent makes use of the >Intel code and data segment descriptors. Segment descriptors are set at system initialization and never changed. The paging unit in the i386/i486 is used to provide protection and process isolation; page tables are manipulated at context switch time, but segment tables are not. This design was chosen for a variety of reasons, particularly performance. -- Jeff Berkowitz N6QOM uunet!sequent!jjb Sequent Computer Systems jjb@sequent.com