wilson@BLAKE.ACS.WASHINGTON.EDU (Wai K. Wilson Fu) (12/31/88)
Hi there,
I have a question from my friend on how the 68030 decode.
The question is:
I have a problem on how the 68030 decodes the instruction sets.
For example, the ADD command, it has Addr Reg Indirect with Index
(8-bit displacement) Mode, Addr Reg Indirect with index (Based
Displacement) Mode, Mem. Indirect Postindexed Mode, Mem Indirect
Preindexed Mode. They all use the same code on the "MODE" and
can be used with all address registers. which means in the code,
it will have the same code:
bit: | 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 |
1 1 0 1 Register OP-mode 1 1 0 Reg-for-EA
(pp 3-18 in the manual). I can't figure out how the microprocessor
decode the instruction.
My response to the question was:
Referring to p. 2-20 and p. 2-18, those four modes in addition to
the instruction format, they also requires one or more extension
words. For the first one of mode 110 which has a 8-bit
displacement indicating that it also has a Brief Format Extension
Word. For the Base Displacement mode, it requires one Full Format
Extension Word while the other two Memory Indirect Modes require
two Extension Words in addition to the instruction format of ADD.
Now for the Memory Indirect Modes, the way to differentiate which
one is which one is by looking at the IS bit and I/IS bit (bit 6
and bits 0-2 of the Full Format, please also refer to Table 2-2)
A Memory Indirect Postindexed mode would have IS=0 and I/IS= 101
or 110 or 111. And a Memory Indirect Preindexed mode would have
IS=0 and I/IS= 001 OR 010 OR 011. Please correct me if make a
mistake here.
Referring to your problem of how to decode it, I really do not
know how the bit map would look like for the Full extension format
words. Please let me know if you figure that out.
The page no. was referring to mc68030 user's manual.
Can someone gives me any hints on how the bitmap would look like for the
Full Extension Format Word or points to to some dirrecton. Any
help would be greatly appreciated.
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