itrctor@csri.toronto.edu (Ron Riesenbach) (06/14/89)
(GB = Gailbraith Building, 35 St. George Street)
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COLLOQUIUM
GB248, at 10:00 a.m., 7 July 1989
Distinguished Guest Speakers
_S_i_g_m_a _D_e_l_t_a _A-_t_o-_D _C_o_n_v_e_r_t_e_r_s _f_o_r _T_e_l_e_c_o_m_m_u_n_i_c_a_t_i_o_n_s _A_p_p_l_i_c_a_t_i_o_n_s
Lectures by two leading experts in Analog-to-Digital Converter Design.
Hosted by Professors Andre Salama and Martin Snelgrove
&
Presented by:
_I_n_f_o_r_m_a_t_i_o_n _T_e_c_h_n_o_l_o_g_y _R_e_s_e_a_r_c_h _C_e_n_t_r_e
Date: Friday, July 7, 1989
Time: 10:00 - 12:00 noon
Location: University of Toronto, Galbraith Bldg. Rm 248, 35 St. George
Street, Toronto.
_S_I_N_G_L_E _B_I_T _S_I_G_M_A _D_E_L_T_A _D_A_T_A _C_O_N_V_E_R_S_I_O_N
_J_e_f_f_r_e_y _W. _S_c_o_t_t, _A_T&_T _B_e_l_l _L_a_b_s
Compared to classical data conversion techniques, single bit oversam-
pled sigma delta architectures offer linearity performance that is indepen-
dent of component matching. The shift in processing burden from the analog
to digital domain that results from the speed/accuracy tradeoff makes CMOS
the technology of choice for sigma delta implementation.
The principle of operation of single and double loop sigma delta con-
verters will be presented, followed by a discussion of CMOS performance and
implementation issues such as noise/linearity limits, DSP complexity, limit
cycle oscillations and higher order loop instability. Particular attention
will be given to production-oriented concerns focusing on the
design/manufacturing cycle time.
The talk will conclude with a discussion of the "extreme" in single
bit architectures - the fourth order interpolative modulator recently pro-
posed by the Massachusetts Institute of Technology.
_D_I_G_I_T_A_L_L_Y _C_O_R_R_E_C_T_E_D _M_U_L_T_I-_B_I_T _S_I_G_M_A _D_E_L_T_A _D_A_T_A _C_O_N_V_E_R_T_E_R_S
_G_a_b_o_r _C. _T_e_m_e_s, _U_n_i_v_e_r_s_i_t_y _o_f _C_a_l_i_f_o_r_n_i_a, _L_o_s _A_n_g_e_l_e_s
Sigma delta data converters using multi-bit internal A/D and D/A con-
verters (noise-shaping converters) have lower quantization noise and are
more stable than the usual single-bit systems. However, the required
linearity of the internal multi-bit DAC is very difficult to achieve for an
untrimmed integrated converter. This paper describes several novel multi-
bit sigma delta converters which use digital correction schemes to cancel
the errors due to the nonlinearity of the internal DAC. Simulation and
experimental results are given. They verify the high accuracy achievable
with the proposed systems.
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This event is free to all industrial affiliates of the ITRC as well as
faculty and students at the participating institutions. Industrial affili-
ates are invited to join the speakers for lunch and a tour of the VLSI
design laboratories after the talks. Industrial affiliates are requested
to register for this event by phoning Rosanna Reid at (416) 978-8558 by
July 4th, 1989.
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