calton@cs.columbia.edu (Calton Pu) (10/18/89)
[ Delayed due to the quake. --DL ]
The executable ready queue is explained in more detail in our SOSP
paper ("Threads and Input/Output in the Synthesis Kernel" by Henry
Massalin and Calton Pu, Proceedings of the Twelfth Symposium on
Operating Systems Principles, December of 1989, traditionally sent to
all SIGOPS members after the conference).
In the paper, Figure 3 shows a simplified version of the code and
table 4 the measured performance on a 68020-based machine equivalent
to SUN-3/160. Quoting from the table 4, context switches of threads
that do not use floating point coprocessor take 11 microseconds and 21
usec for those that use float point coprocessor. I should point out
that Synthesis threads are light-weight and orthogonal to the memory
abstraction. Memory management overhead will add the TLB invalidation
(about 1 usec) and the TLB misses (dependent on the application and
memory access time, approximately 3 usec per miss).
Other recent Synthesis papers:
"Fine-Grain Scheduling" by Henry Massalin and Calton Pu,
Proceedings of the Workshop on Experiences in Building Distributed and
Multiprocessor Systems, October 1989, Usenix Association.
"An Overview of Synthesis", by Calton Pu and Henry Massalin,
Technical Report CUCS-470-89, Dept. Comp. Sci., Columbia University.