[comp.os.research] DineroIII Cache Simulator Description

perform@vuse.vanderbilt.edu (Performance Mailing List) (07/12/90)

        I make dineroIII, the C program described in the attached unix
man page, available to researchers via ftp.  DineroIII allows for the
detailed trace-driven simulation of one cache at a time.
        
        If interested, please send me e-mail (markhill@cs.wisc.edu).
I do NOT have address traces to distribute.
 
                                        --Mark Hill
 
 
 
DINEROIII()         UNIX Programmer's Manual          DINEROIII()
 
 
 
NAME
     dineroIII - cache simulator, version III
 
SYNOPSIS
     dineroIII -b block_size -u unified_cache_size -i
     instruction_cache_size -d data_cache_size [ other_options ]
 
DESCRIPTION
     dineroIII is a trace-driven cache simulator that supports
     sub-block placement.  Simulation results are determined by
     the input trace and the cache parameters.  A trace is a fin-
     ite sequence of memory references usually obtained by the
     interpretive execution of a program or set of programs.
     Trace input is read by the simulator in din format
     (described later).  Cache parameters, e.g. block size and
     associativity, are set with command line options (also
     described later).  dineroIII uses the priority stack method
     of memory hierarchy simulation to increase flexibility and
     improve simulator performance in highly associative caches.
     One can simulate either a unified cache (mixed, data and
     instructions cached together) or separate instruction and
     data caches.
    
     THIS VERSION OF DINEROIII DOES NOT PERMIT THE SIMULTANEOUS
     SIMULATION OF MULTIPLE ALTERNATIVE CACHES.
 
     ...
 
     The command line options include:
 
     -b block_size
 
     -u unified_cache_size
 
     -i instruction_cache_size
 
     -d data_cache_size
 
     -S subblock_size
 
     -a associativity
 
     -r replacement_policy
 
     -f fetch_policy
 
     -w write_policy
 
     -A write_allocation_policy
 
SEE ALSO
     Mark D. Hill, Test Driving Your Next Cache, Magazine of
     Intelligent Personal Systems (MIPS), August 1989, pp. 84-92.
 
     Mark D. Hill and Alan Jay Smith, Experimental Evaluation of
     On-Chip Microprocessor Cache Memories, Proc. Eleventh Inter-
     national Symposium on Computer Architecture, June 1984, Ann
     Arbor, MI, pp. 158-174.
 
AUTHOR
     Mark D. Hill
     Computer Sciences Dept.
     1210 West Dayton St.
     Univ. of Wisconsin
     Madison, WI 53706
     markhill@cs.wisc.edu