detjens@ic.Berkeley.EDU (Ewald Detjens) (04/19/87)
This announcement is being sent to network bulletin boards that we thought would find it of interest. Please let us know if you are interested in participating in this workshop and feel free to forward this announcement to any colleagues that may not have been reached by this posting. Thank you. ******************************************************************************* INITIAL ANNOUNCEMENT Workshop on High-Level Synthesis January 17-20, 1988 (tentative) ******************************************************************************* CALL FOR PARTICIPATION You are invited to participate at the Workshop on High-Level Synthesis to be held January 17-20, 1988. Presentations will focus on the practical use of high-level synthesis tools. A set of example design problems will form the focal point for discussions on the following topics: - high-level specification - hardware description languages - design representation translation - user interfaces for high-level tools - architectural issues - control logic synthesis - data path synthesis - speed/area/power tradeoffs - design style selection - algorithmic vs. rule-based approaches - correctness and verification - simulation and testing The objective of the workshop is to begin the development of a set of "high-level synthesis benchmarks" that can provide a means of comparing different synthesis systems and guide future work to include a complete range of digital circuits. Participants will be asked to relate their work to a set of examples. The presentation should clearly state which examples were chosen and why, what method or language used for their description, and which aspects of the design problem were addressed. Design problems will be described in ISPS or an equally familiar hardware description language. Evaluation of results will be based on design size and complexity as well as elapsed designer time in interaction with the specification and synthesis systems. The following is a list of possible example design problems: - UART - universal asynchronous receiver transmitter - Simple microprocessor (PDP8 or 6502) - Complex processor (VAX or 370) - 68020 to static RAM interface - DMA controller To encourage a free exchange of ideas, no proceedings will be published nor will recording devices be permitted. Materials may be distributed at the discretion of the participant. Sessions will be informal, with adequate time for each presentation to lead to more general discussion. A session at the end of the workshop will be allocated for summary remarks and discussion of future directions. The 1988 Design Automation Conference may provide a forum for the presentation of workshop results. Workshop attendance will be limited to 60. SUBMISSION OF PROPOSALS Participants wishing to deliver a regularly scheduled presentation should submit 5 copies of a maximum 1000-word summary, apart from references and figures, indicating relevancy of the work, current status, and willingness to focus on a subset of the design examples to be provided. TENTATIVE DEADLINES July 15 - Packet of design examples mailed to participants October 30 - Proposals to the workshop or technical chair December 1 - Notification of acceptance December 10 - Mailing of workshop program and registration January 10 - Registration deadline MAILING ADDRESSES Workshop Chair: Ewald Detjens 1820 Carleton Street Berkeley, CA 94703 detjens@ic.berkeley.edu, ucbvax!ucbic!detjens (415) 849-2020 Program Chair: Gaetano Borriello Computer Science Division - 571 Evans Hall University of California Berkeley, CA 94720 gaetano@ucbarpa.berkeley.edu, ucbvax!ucbarpa!gaetano (415) 642-8248 Local Arrangements: Louis Hafer Simon Fraser University Barnaby, BC CANADA lou%sfulccr.can@ubc.csnet (604) 291-4153 *******************************************************************************