[news.announce.conferences] CFP: Conference on Hardware Design and Verification

mrb@sei.cmu.edu (Mario Barbacci) (12/01/87)

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                                CALL FOR PAPERS

                      INTERNATIONAL WORKING CONFERENCE ON

               "THE FUSION OF HARDWARE DESIGN AND VERIFICATION"

                                JULY 4-6, 1988
                           UNIVERSITY OF STRATHCLYDE
                                    GLASGOW
                                   SCOTLAND

The ever-increasing complexity of integrated circuits, coupled with the need to
quickly and accurately produce new designs, has caused a surge of  interest  in
mathematically-based  design  and  validation techniques.  Established software
engineering  techniques  underpinned  by  formal  theories  have  begun  to  be
successfully  applied  to  the  task of verifying design correctness.  Research
into hardware verification has reached a certain  maturity,  and  a  number  of
distinct  approaches  have  recently  emerged.    The  inherent  complexity  of
integrated circuits creates real problems when  verification  is  attempted  on
completed  designs.   A solution to this problem has appeared with the advocacy
of the close integration of design and verification throughout all the steps of
the design process.

The  fusion  of  verification  with  VLSI  design  appears  to  be  a promising
methodology for the future, where the ultimate goal is the inclusion of  formal
verification within CAD systems.  This international working conference aims to
explore  issues  relating  to  the  integration  of  design  and  verification,
including the practical issues of applying formal techniques to CAD.

Topics which the conference will embrace include the following:

                       design and verification languages
                     design and verification methodologies
                      formal verification and simulation
                        verification within CAD systems
                       implementing verification systems
                        behavioral models for hardware
                multi-level simulation within the design cycle
                 behaviorally correct architectural synthesis.

The  working conference is sponsored by IFIP Working Group 10.2, Digital System
Description and Design Tools.  It is the fourth in a series on related areas of
hardware  verification; previous conferences have been held in Darmstadt(1984),
Edinburgh (1985)  and  Grenoble  (1986).    The  objective  to  bring  together
researchers,  developers  and  users  in  this emerging area, with participants
being drawn from the industrial and academic worlds.  It is intended  that  the
conference  be  kept  small  and informal to permit a close interaction between
participants.  Attendance will be by invitation.

If you would like to participate, please submit a  brief  description  of  your
research  interests  to  the Chairman by April 1st, 1988.  If you would like to
make a presentation ( > 1 hour), please submit a paper in English to reach  the
conference Chairman no later than March 1st, 1988.

Following  the review process, notification of the acceptance of papers will be
by April 21st, 1988, with camera-ready manuscripts due on June 7th, 1988.   The
proceedings will be published.

An  opportunity  will  also  exist for short, informal presentations on ongoing
work.  Please indicate to the Chairman your intention to use this facility.

Conference Chairman:               Conference Committee:
George J. Milne                    Francois Anceau, Bull Research
Department of Computer Science     Dominique Borrione, Univ. de Provence
University of Strathclyde          Hans Eveking, T. Hochschule Darmstadt
26 Richmond Street                 George Milne, University of Strathclyde
Glasgow G1 1XH
Scotland, U.K.

phone:  (44) 41 552 4400, ext: 3551.
telex:  77472 (UNSLIB-G).

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