rodrique@hplabsz.HPL.HP.COM (Mike Rodriquez) (03/24/88)
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Advance Program for the
15TH ANNUAL INTERNATIONAL SYMPOSIUM ON
COMPUTER ARCHITECTURE
May 30th - June 3rd, 1988 Ilikai Hotel, Honolulu, Hawaii, USA
Sponsored by
Computer Society of the Institute of Electrical and Electronics Engineers, TCCA
Association for Computing Machinery, SIGARCH
General Chair: H.J. Siegel, Supercomputing Research Center
Program Co-Chairs: Doug DeGroot, Texas Instruments
Yale N. Patt, UC, Berkeley
Symposium Committee:
Finance, Local Arrangements: Mary Jane Irwin, Pennsylvania State Univ.
Tutorials: Shreekant S. Thakkar, Sequent Computer Systems
Student Grants: Mark A. Franklin, Washington Univ.
Registration: Nathanial J. Davis IV, Air Force Institute of Technology
Publicity: Steven P. Levitan, Univ. of Pittsburgh
Proceedings: Jose Fortes, Purdue Univ.
Exhibits: Alan D. Berenbaum, AT&T Information Systems
Audio Visuals: S. Diane Smith, Tesuji
Program Committee:
Jean-Loup Baer, Univ. of Washington Al Despain, UC, Berkeley
Jack Dongarra, Argonne Nat'l Labs Mike Flynn, Stanford Univ.
Gideon Frieder, Syracuse Univ. Dan Gajski, UC, Irvine
Lee Giles, AFOSR Jim Goodman, Univ. of Wisconsin
Bert Halstead, MIT Kai Hwang, Univ. of Southern California
Wen-mei Hwu, Univ. of Illinois Joe Linn, Institute for Defense Analyses
Jack Lipovski, Univ. of Texas Trevor Mudge, Univ. of Michigan
Janak Patel, Univ. of Illinois Andy Pleszkun, Univ. of Wisconsin
Constantine Polychronopolous, U.Ill. Dan Siewiorek, Carnegie-Mellon U.
Dick Sites, DEC Jack Stankovic, Univ. of Massachusetts
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CONFERENCE SCHEDULE
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Monday, May 30, 1988
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9:00 - 10:30am Morning Tutorials
----------------------------
1) Functional Programming and Computer Architecture -- Peter Harrison and
Tony Field (Imperial College)
2) Parallel Processing Networks and Systems -- H.J. Siegel
(Supercomputing Research Center)
3) GaAs Microprocessors: Architecture and Design -- Veljko Milutinovic
(Purdue Univ.)
----------------------------
2:30 - 4:00pm Afternoon Tutorials
----------------------------
4) Logic Programming Architectures -- John Conery (Univ. of Oregon) and
Evan Tick (ICOT)
5) Fine Grained Concurrent Computing -- William Dally and Andrew Chen (MIT)
6) Cache Design for Multiprocessor Systems -- Shreekant Thakkar
(Sequent Computer Systems)
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Tuesday, May 31, 1988
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9:00-10:00 Session 1
----------------------------
Opening Session and Welcome - Keynote Address David J. Kuck,
Super-Computing Research and Development, Univ. Illinois
----------------------------
10:30-12:00 noon Session 2A: Neural Networks and Optical Computing
----------------------------
-Critical Issues in Mapping Neural Networks on Message-Passing
Multicomputers -- Joydeep Ghosh and Kai Hwang (Univ. of Southern California)
-Multinomial Conjunctoid Statistical Learning Machines-- Yoshiyasu Takefuji,
Robert Jannarone, Yong Cho and Tatung Chen (Univ. of South Carolina)
-A Bit-Slice Array Architecture for Optical Computing with 2-D
Symbolic Substitution -- Ahmed Louri and Kai Hwang (Univ. of Southern
California)
----------------------------
10:30-12:00 noon Session 2B: Processor Design
----------------------------
-The Reconfigurable Arithmetic Processor -- Stuart Fiske and William Dally
(MIT)
-The Performance Potential of Multiple Function Unit Processors -- Andrew
Plezskun and Gurindar Sohi (Univ. of Wisconsin)
-Exploiting Single-Chip Parallel Microarchitectures with a Compiler Code
Generator: a Case Study -- Wen-mei Hwu and Pohua Chang (Univ. of Illinois)
----------------------------
2:00-4:00pm Session 3A: Memory Heirarchies
----------------------------
-Analysis of Memory Referencing Behavior for Design of Local Memories --
Geoffrey McNiven and Edward Davidson (Univ. of Illinois)
-Performance Evaluation of On-Chip Register and Cache Organizations
Richard Eickemeyer and Janak Patel (Univ. of Illinois)
-On the Inclusion Properties for Multi-Level Cache Hierarchies --
Jean-Loup Baer and Wen-Hann Wang (Univ. of Washington)
-A Simulation Study of Two-Level Caches -- Robert Short and Henry Levy
(Univ. of Washington and DEC)
----------------------------
2:00-4:00pm Session 3B: Networks - I
----------------------------
-Hyperswitch Network for the Hypercube Computer -- E. Chow, H. Madan,
J. Peterson (JPL), D. Grunwald, D. Reed (Univ. of Illinois)
-Analysis of Bus Heirarchies for Multiprocessors -- Donald C. Winsor
and Trevor N. Mudge (Univ. of Michigan)
-Extra Group Network: A Cost-effective Fault-tolerant Multistage
Interconnection Network -- Sizheng Wei and Gyungho Lee (Univ. of
Southwestern Louisiana)
-A Partial-Multiple-Bus Computer Structure with Improved
Cost-Effectiveness -- Hong Jiang (Univ. of Southwestern Louisiana) and
Kenneth C. Smith (Univ. of Toronto)
----------------------------
4:30-6:00pm Session 4A: Functional/Dataflow Systems
----------------------------
-Flagship: A Parallel Architecture for Declarative Programming -- Ian
Watson, Viv Woods, Paul Watson, Richard Banach, Mark Greenberg, and
John Sargeant (Univ. of Manchester, UK)
-Toward a Dataflow/von Neumann Hybrid Architecture -- Robert Iannucci (MIT)
-Resource Requirements of Dataflow Programs -- David Culler and Arvind (MIT)
----------------------------
4:30-6:00pm Session 4B: Real Time Systems
----------------------------
- Priority-Driven, Preemptive I/O Controllers for Real-Time Systems
-- Brinkley Sprunt, David Kirk and Lui Sha (Carnegie-Mellon Univ.)
-A Kernel-Independent, Pipelined Architecture for Real-Time 2-D
Convolution -- Shridhar B. Shukla and Dharma P. Agrawal (North Carolina
State Univ.)
-Exploiting Bit Level Concurrency in Real-Time Geometric Feature
Extractions -- Wentai Liu and Tong-Fei Yeh (North Carolina State Univ.)
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Wednesday, June 1, 1988
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9:00-10:30am Session 5A: Characterization and Analysis
----------------------------
-Measuring VAX 8800 Performance with a Histogram Hardware Monitor
-- Douglas Clark, Pete Bannon and Jim Keller (DEC)
-Multiprocessor Address Tracing and Characterization Using ATUM -- Anant
Agarwal (Stanford Univ.)
-Trade-offs Between Devices and Paths in Achieving Disk Interleaving
-- Spenser Ng, Robert Selinger and Dorothy Lang (IBM)
----------------------------
9:00-10:30am Session 5B: Numeric Computation
----------------------------
-Design of a Concurrent Computer for Solving Systems of Linear
Equations -- K. Jainandunsing and E. F. Deprettere (Delft Univ. of Technology)
-The White Dwarf: A High-Performance Application-Specific Processor --
A. Wolfe, M. Breternitz, C. Stephens, A. Ting, D. Kirk, R. Bianchini, and
J. Shen (Carnegie-Mellon Univ.)
-Solving Partial Differential Equations in a Data-Driven Multiprocessor
Environment -- J. L. Gaudiot, M. Hosseiniyar and C.M. Lin (Univ. of Southern
California)
----------------------------
11:00am-12:30pm Session 6A: Memory and Communication
----------------------------
-A scrambled storage scheme for parallel memory sytems -- De-lei Lee
(York Univ.)
-The Architecture of a Linda Coprocessor -- Venkatesh Krishnaswamy (Yale Univ.)
----------------------------
11:00am-12:30pm Session 6B: Potpourri
----------------------------
-Deadlock-Avoidance for Systolic Communication -- H.T. Kung
(Carnegie-Mellon Univ.)
-Cache Performance of Vector Processors -- Kimming So and Vittorio Zecca (IBM)
-Distributed First-Come First-Served and Round-Robin Protocols
and their Application to Multiprocessor Bus Arbitration -- Mary Vernon and
Udi Manber (Univ. of Wisconsin)
----------------------------
2:30-4:30pm Session 7A: Caches
----------------------------
-Scalable Directory Schemes for Cache Coherence -- Anant Agarwal, Richard
Simoni, John Hennessy and Mark Horowitz (Stanford Univ.)
-Performance Tradeoffs in Cache Design -- Steven Przybylski, Mark Horowitz
and John Hennessy (Stanford Univ.)
-Cache Coherence Scheme With Fast Selective Invalidation -- Hoichi Cheong and
Alexander Veidenbaum (Univ. of Illinois)
-An Accurate and Efficient Performance Analysis Technique for Multiprocessor
Snooping Cache-Consistency Protocols -- Edward Lazowska, Mary Vernon, and
John Zahorian (Univ. of Washington)
----------------------------
2:30-4:30pm Session 7B: Networks - II
----------------------------
-Destination Tag Routing Techniques Based on a State Model for the
IADM Network -- Darwen Rau, Jose Fortes (Purdue Univ.) and H.J. Siegel (SRC)
-Regular CC-Banyan Networks -- D.W. Kim, G.J. Lipovski (The Univ. of Texas),
A. Hartmann (MCC) and Roy M. Jenevein (The Univ. of Texas)
-Traffic Analysis of Rectangular SW-Banyan Networks
Roy M. Jenevein and Thomas Mookken (The Univ. of Texas)
-High-Performance Multi-Queue Buffers for VLSI Communication Switches --
Yuval Tamir and Gregory Frazier (UCLA)
----------------------------
5:00-6:30pm Session 8: Panel on Future Technologies
----------------------------
Chairman: C. Lee Giles (Air Force Office of Scientific Research).
Panelists: Bidock Bidard (DOD) "Superconductivity," Sadik Esner (Dept. of
EE&CS, UCSD, Call-Recall, Inc.) "3-D Memory," Alan Huang (AT&T Bell Labs)
"Optical Computing Architectures," Larry Jackel (AT&T Bell Labs) "Electronic
Neural Networks."
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Thursday, June 2, 1988
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9:00-10:30am Session 9A: Multiprocessors - I
----------------------------
-A Cache-based Message Passing Scheme for a Shared-bus
Multiprocessor -- Bruno R. Preiss (Univ of Waterloo) and V. Carl
Hamacher (Univ. of Toronto)
-IMPULSE: A High Performance Processing Unit for A Multiprocessor for
Scientific Calculations -- Taisuke Boku, Shigehiro Nomura, and Hideharu Amano
(Keio Univ.)
-Characterization of Sharing in Parallel Programs and Its
Applicability to Coherency Protocol Evaluation -- Susan Eggers and Randy Katz
(UC, Berkeley)
----------------------------
9:00-10:30am Session 9B: Synchronization Mechanisms
----------------------------
-A Fetch-and-Op Implementation for Parallel Computers -- G.J. Lipovski and
Paul Vaughan (The Univ. of Texas)
-Synchronizing Processors through Memory Requests in a Tightly-coupled
Multiprocessor -- Andre Seznec and Yvon Jegou (IRISA/INRIA)
-Design and Performance of Special Purpose Hardware for Time Warp --
Richard M. Fujimoto, Jya Tsai, and Gnesh Gopalakrishnan (Univ. of Utah)
----------------------------
11:00am-12:30pm Session 10A: Multiprocessors - II
----------------------------
-The VMP Multiprocessor: Initial Experience, Refinement and Performance
Evaluation -- David Cheriton, Anoop Gupta, Patric Boyle, and Hendrick Goosen
(Stanford Univ.)
-The Wisconsin Multicube: A New Large Scale Cache-Coherent Multiprocessor --
James Goodman and Philip Woest (Univ. of Wisconsin)
----------------------------
11:00am-12:30pm Session 10B: AI Systems
----------------------------
-Data Buffer Performance for Sequential Prolog
Architectures -- Evan Tick (Stanford Univ.)
-MASA: A Multithreaded Processor Architecture for Parallel
Symbolic Computing -- Robert H. Halstead, Jr. (MIT) and Tetsuya Fujita (NEC)
-Network Architecture for OPS5 -- P.L. Butler, J.D. Allen, and
D.W. Bouldin (Univ. of Tennessee)
----------------------------
2:00-3:30pm Session 11: Panel on the Future of Parallel Processing
----------------------------
Chairman: Andre van Tilborg (Office of Naval Research).
Panelists: Jack Dennis (MIT Lab for CS), H.T. Kung (Carnegie-Mellon Univ),
Burton Smith (Tera Computer), Harold Stone (IBM Research Center, Courant Inst.)
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Friday, June 3, 1988
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9:00am - 12:30pm Full Day Tutorial
----------------------------
Neural Networks -- Clif Penn (Texas Instruments)
----------------------------
2:00-5:30pm Full Day Tutorial con't.
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FOR REGISTRATION INFORMATION SEE THE APRIL ISSUE OF COMPUTER MAGAZINE
OR CONTACT ACM/IEEE-CS 15TH ISCA, P.O. BOX 12105, CHURCH STREET STATION,
NEW YORK, NY, 10249. (212) 869-7440.
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AVE., P.O. BOX 2198 W. LAFAYETTE, IN, 47906. (800) 227-7477, (317) 743-2116.
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