mslater@cup.portal.com (09/24/88)
*********** M I C R O P R O C E S S O R S ' 8 9 **********
What: A one-day symposium on high-performance
microprocessors and system design.
When: November 3, 1988, from 8 am to 6 pm.
Where: Red Lion Inn, San Jose, California.
Why: To explore the issues facing designers of high-
performance microprocessor-based systems. To understand the
impact of RISC architectures and the future of CISC. And
for a preview of the key developments to occur in 1989.
Who: Mitch Alsup, Motorola
John Crawford, Intel
Dave Ditzel, Sun Microsystems
Mike Johnson, AMD
Steven McGeady, Intel
Dave Mothersole, Motorola
Chris Rowen, MIPS Computer Systems
Kim Rubin, VME Specialists
David Schanin, National Semiconductor
Michael Slater, Microprocessor Report
Nick Tredennick
******************* P R O G R A M ********************
8:00 -- 8:30 Registration
8:30 -- 12:00 Dave Ditzel, Sun Microsystems
Past and Future SPARC Implementations
Chris Rowen, MIPS Computer Systems
Balanced High-Performance RISC Design
Mitch Alsup, Motorola
System Design with the 88000
Mike Johnson, AMD
AMD's 29000 Provides Memory System Versatility
Steve McGeady, Intel
Intel's 80960 Delivers Performance in Embedded Systems
12:00 -- 1:15 Lunch
1:15 -- 3:00 Kim Rubin, VME Specialists
Making It All Work: A System Designer's Perspective
Nick Tredennick
Where Microprocessor Design is Heading
Michael Slater, Microprocessor Report
An Advance Look at the Next Generation of Microprocessors
3:00 -- 5:00 Panel Discussion
Above speakers to be joined by:
John Crawford, Intel
David Schanin, National Semiconductor
David Mothersole, Motorola
5:00 -- 6:00 Reception
***************** About the Speakers ********************
Mitch Alsup, the chief architect of Motorola's 88000, is
currently working on future generations of that
architecture. Before joining Motorola, he developed
languages, compilers, and interpreters for Gould Computer
Systems and NCR.
John Crawford, who was the chief architect of Intel's 80386
from 1982 until its introduction, is now working on the 486.
Prior to his work on the 386, he worked in compiler
development at Intel. He is the author of Programming the
80386.
Dave Ditzel is Manager of Advanced CPU Architectures at Sun
Microsystems. At present, he is working on the design of
high-performance SPARC-based computers. Before coming to
Sun, he was at Bell Labs as one of the principal designers
of AT&T's CRISP microprocessor.
Mike Johnson was the chief architect of AMD's 29000 product
family. In parallel with his efforts on the 29000, he is
conducting research into superscalar architectures. Prior
to joining AMD, he spent 8 years at IBM, and worked on IBM's
ROMP processor design.
Steven McGeady is one of the original members of the 80960
design team, and currently is program manager for the 80960
Software Development Tools group. Before joining Intel, he
was with Tektronix as a project leader on a graphics display
system for a UNIX workstation.
Dave Mothersole is the manager of Motorola's 68000
development group. He was the project leader for the 68020
design team, and the design manager on the 68030 project.
Before joining Motorola, he worked for IBM as a software
engineer.
Chris Rowen is the Director of Interactive Systems at MIPS
Computer Systems, where he has been responsible for the
design and development of key computer systems. At Stanford,
he was intimately involved with specifying the MIPS RISC
architecture. Prior to joining MIPS, he worked on static
RAMs and microprocessor technology at Intel.
Kim Rubin is the Vice President, Engineering at VME
Specialists, where he is responsible for developing new VME
products. Before joining VME Specialists, he was Director of
Engineering for Force Computers' U.S. operations, where he
designed a high-performance 386-based VME CPU. Prior to his
work at Force, he designed data compression and expansion
hardware for Integrated Automation.
David Schanin is the Chief Scientist and Technical Director
for National's 32000 architecture. He was the president and
founder of Hydra Computer Systems and the chief architect of
the Encore MultiMax computer system. Before founding Hydra,
he spent 8 years at DEC developing multiprocessor machines.
Michael Slater is the Editor and Publisher of Microprocessor
Report, a monthly newsletter for designers of
microprocessor-based systems. He also lectures at Stanford,
teaches technology classes for Silicon Valley firms, and
consults on the design of microprocessor-based hardware.
Prior to founding his consulting business, he worked at
Hewlett-Packard as an R & D engineer. He is the author of
Microprocessor-Based Design, a standard reference text.
Nick Tredennick managed the design of Nexgen Microsystems'
F86 chip set, a multi-chip implementation of the 386
architecture. While at IBM, he designed the logic and
microcode for the System/370 microprocessor. At Motorola, he
designed the microprogrammed controller for the 68000. He
is the author of the text Microprocessor Logic Design.
****************** About the Symposium ******************
A new wave of microprocessors is upsetting the balance of
power among IC manufacturers. In terms of performance, RISC
microprocessors have leapfrogged the established 80x86 and
680x0 architectures. However, RISC systems often require
expensive cache subsystems, and they're more difficult to
design. The battle lines are still being drawn, and CISC
architectures promise to fight back in the next generation.
The CPU wars are intensifying, and 1989 is shaping up as a
critical year with the expected introduction of major new
microprocessors, including:
Intel's 80486
Motorola's 68040
National's 32764
Non-Intel multichip implementations of the 386
architecture
New, more highly integrated implementations of the
SPARC architecture
An enhanced version of AMD's 29000
New implementations of Intel's 80960 architecture
Many of the new chips will include on-chip floating-point,
memory management, and cache memory. Additional on-chip
parallelism will reduce the average number of clocks per
instruction for both RISC and CISC processors.
The sheer number of new microprocessors, their increasing
complexity, the importance of software support, and the web
of partnerships and licensing agreements make it harder than
ever to make informed design decisions.
Do you need to know where microprocessors are heading?
To get on the inside track, come to Microprocessors '89.
You'll hear carefully chosen speakers who are technical
experts, innovators, and good communicators. People with
clear visions of the future of microprocessors. Not
everyone has the same vision, of course, and you'll hear a
variety of viewpoints. No marketing pitches. No sales
hype.
In the morning, you'll hear presentations by RISC
microprocessor architects from Intel, Motorola, AMD, Sun,
and MIPS. After lunch you'll get independent perspectives
from three speakers who aren't associated with any
semiconductor vendor. And finally, designers representing
each of the major CISC architectures will join the speakers
for a panel discussion about the future of microprocessor
systems.
The panel will welcome questions from the audience, and
you'll also have a chance to talk directly with the speakers
over lunch and at a reception at the end of the day. This
one-day symposium is a rare opportunity to meet the leaders
in microprocessor design. You won't want to miss it.
Advance registration is required. The registration fee is
$175 for subscribers to Microprocessor Report and $275 for
non-subscribers. The fee covers the entire day, including
lunch and reception. Handout materials for each registrant
will include technical data from all of microprocessor
manufacturers represented at the symposium.
Microprocessors '89 is sponsored by MicroDesign Resources,
Inc., publisher of Microprocessor Report.
Send in your registration today! Space is limited, and the
registration deadline is October 20.
Credit cards and purchase orders accepted.
******************* Topics include: *******************
o The major new 32-bit microprocessors and what it takes to
put systems together around them
o How to tune system designs for optimum performance by
balancing processor, bus, memory, and I/O system speeds
o Strengths and weaknesses of CISC and RISC architectures
o How the next-generation CISC processors will incorporate
RISC techniques
o Use of multiple instruction pipelines and other
techniques for executing more than one instruction per
clock
o System partitioning alternatives for cache, memory
management, and floating-point.
o Techniques for speeding procedure calls and task
switching, including register windows, register caches,
and other types of register files
o Cache memory design for multiprocessor systems
o High-performance coprocessor interfacing -- why on-chip
floating point isn't necessarily faster
******** Microprocessors '89 Registration Form *************
Registration Deadline: October 20, 1988
Name ________________________________ Title ________________
Company ____________________________________________________
Address ____________________________________________________
City ____________________________ State _______ Zip ________
Telephone ____________________________
__ I'm a Microprocessor Report subscriber ............. $175
__ I'm not a subscriber ............................... $275
__ I'm not yet a subscriber, but sign me up for a one-year
subscription ($197) and register me at the subscriber
rate ($175) ........................................... $372
__ Please register ___ additional attendees from our
company (attach list of names) for $200 each. ....... ______
Total Amount ........................................ ______
__ Check enclosed
__ Charge my Mastercard, VISA, or AMEX:
Card number ________________________ Expires ______
Signature _________________________________________
__ Bill my company: P.O. Number ______________________
Registration includes handout materials, lunch, and
reception.
Send completed registration form to:
Microprocessor Report
550 California Avenue, Suite 320
Palo Alto, CA 94306
Or call us with your credit card or purchase order number at
(415) 494-2677. (Or send email to mslater@cup.portal.com)
Accomodations
Microprocessors '89 will be held November 3, 1988 at the Red
Lion Inn, 2050 Gateway Place, San Jose, CA 95110; (408) 279-
0600. A block of rooms has been reserved for attendees
requiring overnight accomodations. When you call the Red
Lion Inn for reservations, tell the agent you're attending
Microprocessors '89 to get the special group rate of $84 per
night. Availability of reservations cannot be guaranteed
after October 15.
Cancellation Policy
A full refund will be provided for cancellations received by
October 20; 50% refund if after 10/20 but before 10/27; no
refunds for cancellations after 10/27 and for no-shows.