mrb@sei.cmu.edu (Mario Barbacci) (02/11/89)
C A L L F O R P A P E R S IFIP WG 10.2-10.5 International Workshop on: APPLIED FORMAL METHODS FOR CORRECT VLSI DESIGN. 13-16 November 1989. imec Interuniversity Micro-Electronics Center Leuven Belgium Objectives ------------------------------------------------------------------------------ This workshop is organized within the scope of IFIP WG 10.2 System Descrip- tion and Design Tools in cooperation with IFIP WG 10.5 Very Large Scale Inte- gration. It is the fifth in a series organized by IFIP WG 10.2 on related areas of correct hardware design and verification. Previous conferences have been held in Darmstadt (1984), Edinburgh (1985), Grenoble (1986), Glasgow (1988). Functional and behavioral verification of the correctness, is the bottle- neck of current VLSI design systems. For economical reasons, designs of VLSI circuits must be completely validated before manufacturing. Current VLSI vali- dation is mainly done through extensive simulation. The emerging alternative is based on formal design and verification methods, that guarantee correct- ness. The aim of this workshop is to bring together all researchers, both from academia and industry, interested in formal hardware design methods that are applicable for correct VLSI design. In order to achieve this, tutorials, exten- ded in-depth overviews and demonstrations of CAD-tools making use of formal methods will be organized as well as regular presentations on current research work. The organization of practical demonstrations as well as presentations will allow for more detailed informal contacts and discussions. Regular presentations ------------------------------------------------------------------------------ Papers describing original work in all aspects of formal hardware design methods are invited. Topics include, but are not limited to: . formal hardware verification methods . guided synthesis methods . high level specification . hardware description languages . use of theorem provers for verification . Boolean provers and tautology checking . MOS timing verification algorithms . switch level verification methods . RTL level verification . use of functional languages . correctness preserving transformations . formal proof of correctness . design for verifyability . practical experiences Prospective authors are invited to submit 3 copies of a paper, not exeeding 20 double spaced typewritten pages, to the Workshop Organizer by 1 July 1989. The proceedings will be published. Demonstrations ------------------------------------------------------------------------------ Proposals are invited for 30' presentations and accompanying demonstrations of CAD programs and prototype tools that illustrate recent research results or original realizations in the area of formal hardware design methods. The pro- posal can either be a short description of the demonstration or can be in the form of a regular presentation as described above. Proposals should be sent to the Workshop Organizer before 1 July 1989. Workstations will be made available on the conference site for demonsta- tions. Authors' schedule ------------------------------------------------------------------------------ . 1 July 1989 : Deadline for submission of papers . 15 September 1989 : Notification of acceptance . 15 October 1989 : Camera-ready paper Tutorials and in-depth Overviews ------------------------------------------------------------------------------ During the workshop, tutorials, as well as more in-depth overviews on applied methods for formal hardware verification and design will be organized. Benchmarking ------------------------------------------------------------------------------ A set of benchmarks for formal verification between RTL specification and hardware implementation will be made available to interested participants. In- terested participants are invited to relate the practical benchmarks to their own work. These will form the focus point for special sessions with compari- sons on methods used. Participation ------------------------------------------------------------------------------ The intention of this workshop is to familiarize the participants with the current state of the art, and new directions of research in applied formal methods for hardware design. Therefore, subscriptions for participation should be made in time. Preregistrations by 1 October 1989. Program Commitee ------------------------------------------------------------------------------ Prof. F. Anceau (BULL FR) Prof. D. Borrione (IMAG Grenoble FR) Prof. R. Bryant (Carnegy Mellon University USA) Dr. L. Claesen (IMEC Leuven B) Dr. H. Eveking (Technische Hochschule Darmstadt FRG) Prof. M. Gordon (University of Cambridge UK) Prof. G.J. Milne (University of Strathclyde UK) Prof. P. Prinetto (Politecnico di Torino IT) Dr. P.A. Subrahmanyam (AT&T Holmdell USA) ------------------------------------------------------------------------------ Workshop Organizer: WG 10.5 representative: Luc Claesen Erik Schutz IMEC vzw MIETEC nv Kapeldreef 75, Westerring 15 B-3030 Leuven Belgium B-9700 Oudenaerde Belgium tel: +32-16-281203 tel: +32-55-332211 fax: +32-16-229400 email: claesen@imec.uucp ------------------------------------------------------------------------------ Name: _____________________________________________________________ Address: _____________________________________________________________ _____________________________________________________________ O Please put me on the mailing list Please reply to: O I am interested in participating Luc Claesen O I am interested in presenting a paper IMEC vzw O I am interested in benchmarking Kapeldreef 75 O I want to give a tutorial B-3030 Leuven O I am prepared to give a demonstration Belgium