gabriels@k.gp.cs.cmu.edu (Gabriel Silberman) (03/04/89)
ADVANCE PROGRAM
The 16th Annual International Symposium on Computer Architecture
May 28th - June 1st, 1989
Hyatt Regency Hotel, Jerusalem, Israel
sponsored by
Computer Society of the Institute of Electrical and
Electronics Engineers - TCCA
and
Association for Computing Machinery - SIGARCH
STEERING COMMITTEE
D. DeGroot, TI
Z. Segall, CMU
Y.N. Patt, UC Berkeley
SYMPOSIUM COMMITTEE
General Co-Chairs
M. Yoeli, Technion
G.M. Silberman, Technion
Vice-Chairs, USA
G. Frieder, Syracuse U.
Z. Barzilai, IBM PROGRAM COMMITTEE
Vice-Chair, Europe M. Amamiya, Japan
U. Trottenberg, SUPRENUM FRG H. Amano, Japan
J.P. Banatre, France
Vice-Chair, Far-East D. Comte, France
Y. Tohma, Tokyo Inst. of Tech. E. Davidson, USA
J. Goodman, USA
Program Chair A. Goto, Japan
J.C. Syre, ECRC A. Gottlieb, USA
A. Hattori, Japan
Program Vice-Chair, USA R.N. Ibbeth, UK
Arvind, MIT C.R. Jesshope, UK
R. Keller, USA
Program Vice-Chair, Europe/Israel T. Knight, USA
J. Gurd, U. Manchester N. Koike, Japan
I. Koren, USA
Program Vice-Chair, Far-East D. Lawrie, USA
M. Kitsuregawa, U. Tokyo S. Nagashima, Japan
J. Noye, FRG
Posters Chair E. Odijk, Netherlands
B. Atlas, Technion K.H. Park, Korea
Y.N. Patt, USA
Finance & Local Arrangements Chair B.R. Rau, USA
R. Ginosar, Technion R.D. Rettberg, USA
L. Roncarolo, Italy
Registration & Travel Grants Chair S. Ruhman, Israel
I. Spillinger, Technion K. Shibayama, Japan
H. Tanaka, Japan
Publicity & Publications Chair S. Tomita, Japan
U. Weiser, INTEL U. Weiser, Israel
T. Yuba, Japan
Tutorials Chair
D. Tabak, GMU
Exhibits Chair
H. Azaria, BGU
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SCHEDULE
Sunday, May 28, 1989. Tutorials at Beit Meirsdorf.
08.00 - 09.00 Registration and Coffee
09.00 - 10.30 Tutorial #1, Designing High Yield VLSI Systems,
I. Koren, UMass Amherst.
09.00 - 10.30 Tutorial #3, RISC Systems, Architecture and
Implementation, V. Milutinovic, Purdue Univ. and
D. Tabak, GMU.
10.30 - 11.00 Coffee Break
11.00 - 12.30 Tutorials #1, #3 continued
12.30 - 14.30 Lunch Break (on your own)
14.30 - 16.00 Tutorial #3 continued
14.30 - 16.00 Tutorial #2, Parallel Processing Systems, H.J. Siegel,
Purdue Univ.
16.00 - 16.30 Coffee Break
16.30 - 18.00 Tutorials #2, #3 continued.
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19.00 - 21.00 Symposium Registration at Hyatt Regency Hotel
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Monday, May 29.
08.00 - 12.00 Registration
09.00 - 11.00 Opening Session
Chair: G.M. Silberman/ M. Yoeli, Technion
Opening Address: Trends in Technology and Systems,
John A. Darringer, IBM Research
Keynote Address: The Evolution to Post-RISC Architectures,
Michael W. Blasgen, IBM Research
11.00 - 11.30 Coffee Break
11.30 - 13.00 Session 2A
Cache Coherence and Synchronization I
Chair: M. Dubois, USC
- Evaluating the Performance of Four Snooping Cache
Coherency Protocols, S.J. Eggers, R.H. Katz, UC Berkeley.
- Multilevel Shared Caching Techniques for Scalability
in VMP-MC, D.R. Cheriton, H.A. Goosen, P.D. Boyle,
Stanford Univ.
- Design and Performance of a Coherent Cache for
Parallel Logic Programming Architectures, A. Goto,
A. Matsumoto, E. Tick, ICOT Tokyo.
11.30 - 13.00 Session 2B
Dataflow
Chair: I. Koren, UMass Amherst
- The Epsilon Dataflow Processor, V.G. Grafe, Sandia
Nat. Lab. Albuquerque.
- An Architecture of a Dataflow Single Chip Processor,
S. Sakai, Y. Yamaguchi, K. Hiraki, Electrotechnical
Lab., Ibaraki Japan.
- Exploiting Data Parallelism in Signal Processing
on a Dataflow Machine, P. Nitezki, FZI, Karlsruhe.
13.00 - 14.30 Lunch Break
14.30 - 16.00 Session 3A
Pipeline Architectures
Chair: A. Gottlieb, NYU
- Architectural Mechanisms to Support Sparse Vector
Processing, R.N. Ibbett, T.M. Hopkins, K.I.M. McKinnon,
Univ. Edinburgh.
- A Dynamic Storage Scheme for Conflict-Free Vector
Access, D.T. Harper III, D.A. Linebarger, Univ.
Texas Dallas.
- SIMP Simple Instruction Stream/Multiple Instruction
Pipelining: A Novel High-Speed Single-Processor
Architecture, K. Murakami, M. Kuga, S.Tomita,
Kyushu Univ.
14.30 - 16.00 Session 3B
Mapping Algorithms
Chair: A.L. Davis, HP
- SIMD Algorithms for 2-D Arrays in Shuffle Networks
Y. Ben-Asher, D. Egozi, A. Schuster, Hebrew Univ.
- Systematic Hardware Adaption of Systolic Algorithms,
M. Valero-Garcia, J.J. Navarro, J.M. Llaberia,
M. Valero, Univ. Politecnica, Barcelona.
- Subcube Allocation and Task Migration in Hypercube
Multiprocessors, M.-S. Chen, K.G. Shin, Univ.
Mich. Ann Arbor.
16.00 - 16.30 Coffee Break
16.30 - 18.00 Panel Session I
Chair: Andre M. van Tilborg, ONR
Choosing a Parallel Paradigm: SIMD or MIMD?
19.30 - CHEESE AND WINE RECEPTION
20.30 - SIGARCH Business Meeting
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Tuesday, May 30.
08.00 - 10.00 Registration
09.00 - 11.00 Session 4A
Uniprocessor Caches
Chair: D. Alpert, INTEL
- Characteristics of Performance-Optimal Multi-Level
Cache Hierarchies, S. Przybylski, J. Hennessy,
M. Horowitz, Stanford Univ.
- Supporting Reference and Dirty Bits in SPUR's
Virtual Address Cache, D.A. Wood, R.H. Katz, UC Berkeley.
- Inexpensive Implementations of Set-Associativity,
R.E. Kessler, Univ. Wisc. Madison.
- Organization and Performance of a Two-Level
Virtual-Real Cache Hierarchy, W.-H. Wang,
J.-L. Baer, H.M. Levy, Univ. Wash. Seattle.
09.00 - 11.00 Session 4B
Networks
Chair: H.J. Siegel, Purdue Univ.
- High Performance Communications in Processor Networks,
C.R. Jesshope, I. McNally, P.R. Miller, J.T. Yantchev,
Univ. Southampton.
- Introducing Memory into the Switch Elements of
Multiprocessor Interconnection Networks, H.E. Mizrahi,
J.-L. Baer, E.D. Lazowska, J. Zahorjan, Univ. Wash. Seattle.
- Using Feedback to Control Tree Saturation in
Multistage Interconnection Networks, S. Scott,
G.S. Sohi, Univ. Wisc. Madison.
- Constructing Replicated Systems Using Processors
with Point-to-Point Communication Links, P.D. Ezhilchelvan,
S.K. Shrivastava, A. Tully, Univ. Newcastle Upon Tyne.
11.00 - 11.30 Coffee Break
11.30 - 12.30 Session 5
Invited Speaker: Mario Tokoro, Sony Corp. and Keio Univ.
Concurrent Objects: A Way to Efficiently
Utilize Hardware Parallelism.
12.30 - 14.00 Lunch Break
14.00 - 16.00 Session 6A
Prolog Architectures
Chair: R. Ginosar, Technion
- KCM: A Knowledge Crunching Machine, H. Benker,
Beacco, Bescos, Dorochevsky, Jeffre, Poehlmann,
Noye, Sexton, Syre, Thibault, Watzlawik, ECRC Munich.
- A High Performance Prolog Processor with Multiple
Function Units, A. Singhal, Y.N. Patt, UC Berkekey.
- Evaluation of Memory System for Integrated Prolog
Processor IPP, M. Morioka, S. Yamaguchi, T. Bandoh, Hitachi.
- A Type Driven Hardware Engine for Prolog Clause
Retrieval over a Large Knowledge Base, K.-F. Wong,
M.H. Williams, Heriot-Watt Univ. Edinburgh.
14.00 - 16.00 Session 6B
Instruction Fetching
Chair: I. Spillinger, Technion
- Comparing Software and Hardware Schemes for
Reducing the Cost of Branches, W.-M.W. Hwu, T.M.
Conte, P.P. Chang, Univ. Ill. Urbana.
- Improving Performance of Small On-Chip Instruction
Caches, M.K. Farrens, A.R. Pleszkun, Univ. Wisc. Madison.
- Achieving High Instruction Cache Performance with
an Optimizing Compiler, W.-M.W. Hwu, P.P. Chang,
Univ. Ill. Urbana.
- The Impact of Code Density on Instruction Cache
Performance, P. Steenkiste, CMU.
16.30 - 19.30 Old City Tour
20.30 - Banquet and Eckert-Mauchly Award Ceremony
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Wednesday, May 31.
08.00 - 10.00 Registration
09.00 - 11.00 Session 7A
Parallel Architectures
Chair: H. Muehlenbein, GMD
- Can Dataflow Subsume von Neumann Computing?, R.S. Nikhil,
Arvind, MIT.
- Exploring the Benefits of Multiple Hardware Contexts
in a Multiprocessor Architecture: Preliminary Results,
W.-D. Weber, A. Gupta, Stanford Univ.
- Architectural and Organizational Tradeoffs in the
Design of the MultiTitan CPU, N.P. Jouppi, DEC Palo Alto.
- Run-Time Checking in Lisp by Integrating Memory
Addressing and Range Checking, M. Sato, S. Ichikawa,
E. Goto, JRDC Tsukiji Tokyo.
09.00 - 11.00 Session 7B
Performance Evaluation
Chair: D.P. Siewiorek, CMU
- Multiple vs. Wide Shared Bus Multiprocessors,
A. Hopper, A. Jones, D. Lioupis, Olivetti Research
Cambridge UK.
- Performance Measurements on a Commercial Multiprocessor
Running Parallel Code, M. Annaratone, R. Ruehl, ETH Zurich.
- Interprocessor Communication Speed and Performance
in Distributed Memory Parallel Processors,
M. Annaratone, C. Pommerell, R. Ruehl, ETH Zurich.
- Analysis of Computation-Communication Issues in
Dynamic Dataflow Architectures, D. Ghosal, S.K. Tripathi,
Univ. Maryland College Park.
11.00 - 11.30 Coffe Break
11.30 - 12.30 Session 8A
Logic Simulation Systems
Chair: E. Kronstadt, IBM
- Logic Simulation on Massively Parallel Architectures,
S.A. Kravitz, R.E. Bryant, R.A. Rutenbar, CMU.
- R256: A Research Parallel Processor for Scientific
Computation, T. Fukazawa, T. Kimura, Y. Itoh, K. Takeda,
M. Tomizawa, NTT.
11.30 - 12.30 Session 8B
Special Purpose Architectures
Chair: S. Ruhman, Weizmann Institute
- A Three-Port/Three-Access Register File for Concurrent
Processing and I/O Communication in a RISC-Like Graphics
Engine, M.L. Anido, D.J. Allerton, E.J. Zaluska,
Univ. Southampton.
- An Architectural Framework for Application-Specific
and Scalable Architectures, J.M. Mulder, R.J. Portier,
A. Srivastava, R. Velt, Delft Univ. of Technology.
12.30 - 14.00 Lunch Break
14.00 - 15.30 Session 9A
Memory Systems
Chair: G. Frieder, Syracuse Univ.
- Perfect Latin Squares and Parallel Array Access,
K. Kim, P. Kumar, USC.
- A Non-Periodic Storage Scheme to Reduce Memory
Conflicts in Vector Processors, S. Weiss,
Univ. of Maryland Baltimore.
- Analysis of Vector Access Performance on Skewed
Interleaved Memory, C.-L. Chen, C.-K. Liao,
Nat. Univ. Taiwan.
14.00 - 15.30 Session 9B
Cache Coherence and Synchronization II
Chair: J. Goodman, Univ. Wisc. Madison
- Adaptive Backoff Synchronization Techniques,
A. Agarwal, M. Cherian, MIT.
- A Cache Consistency Protocol for Multiprocessors
with Multistage Networks, P. Stenstroem, Lund Univ.
- On Data Synchronizations for Multiprocessors,
H.-M. Su, P.-C. Yew, Univ. Ill. Urbana.
15.30 - 16.00 Coffee Break
16.00 - 17.30 Panel Session II
Chair: Abraham Waksman, AFOSR
Hardware and Software Architectures for Real-Time Computing
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Thursday, June 1, 1989. Tutorials at Beit Meirsdorf.
08.00 - 09.00 Registration and Coffee
09.00 - 10.30 Tutorial #4, Advanced Computer Architecture,
D.P. Agrawal, North Carolina State Univ.
09.00 - 10.30 Tutorial #6, Dataflow vs. von Neumann: Two Ends
of a Spectrum, L. Bic, UC Irvine, and J.L. Gaudiot, USC.
10.30 - 11.00 Coffee Break
11.00 - 12.30 Tutorials #4, #6 continued
12.30 - 14.30 Lunch Break (on your own)
14.30 - 16.00 Tutorial #5, Cache Memories, A.J. Smith, UC Berkeley.
14.30 - 16.00 Tutorial #6 continued
16.00 - 16.30 Coffee Break
16.30 - 18.00 Tutorials #5, #6 continued