[news.announce.conferences] Microprocessor Forum Final Program

mslater@cup.portal.com (09/11/89)

*** FINAL PROGRAM: Second Annual Microprocessor Forum ***

           Sponsored by Microprocessor Report

                September 21 and 22
            Fairmont Hotel, San Jose, CA

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Thursday, September 21

Perspective

   The State of the Microprocessor Industry
   Michael Slater, Microprocessor Report

   Keynote 1: The Next Decade of RISC
   John Hennessy, Stanford University / MIPS

New Microprocessors --- RISCs for Workstations

   The i860
   Sai-Wai Fu, Intel

   IBM's Next-Generation RISC Architecture
   Phil Hester, IBM

   An ECL SPARC Chip Set
   Jim Peterson, Bipolar Integrated Technology

   A Custom SPARC Processor
   Mike Schumacher, Solbourne Computer

   A Multiprocessor Cache for SPARC
   Roger Ross, Ross Technology

   Panel: The Future of RISC Processors
   Above speakers plus John Mashey (MIPS), Chuck Corley (Motorola),
   Harlan McGhan (Intergraph), and Michael Mahon (Hewlett-Packard)

Lunch: Alternatives to Random Logic
  Film, followed by panel discussion with Ted Hoff
  and Masatoshi Shima

New Microprocessors --- Revenge of the CISCs

   The 68040
   Dave Mothersole, Motorola

   The 486
   John Crawford, Intel

   Outdoing the 486
   Dave Stiles, Nexgen Microsystems

   The VM8600 Family:  Application Specific Integrated
   Processors
   Masatoshi Shima, V.M. Technology

   Panel: The Future of CISC Processors
   Above speakers plus Guy Harriman (now with NeXT, formerly
   with Inmos) and Phil Downing (Zilog)

   Debate: RISC vs. CISC for the Mainstream Workstation Market
   Roger Ross (Ross Technology) vs. Morris Jones (Chips &
   Technologies)

Benchmarking and Performance Measurement

   An Overview of Common Benchmarks
   Reinhold Weicker, Siemens

   Evaluating RISC and CISC Processor Performance
   Bud Funk, Unisys

   Panel: Fair Benchmarking
   Above speakers plus Jim Geers (AIM Technology), John Mashey
   (MIPS), Dave Ditzel (Sun), and Dave Mothersole (Motorola)

Reception and Microprocessor Chip Plot Exhibition

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Friday, September 22

   Keynote 2: RISC --- An Exercise in Degrees of Freedom
   Andrew Heller, Kleiner, Perkins, Caufield & Byers / Consultant

System Designer Perspectives --- Workstations

   The SPARCstation 1
   Andy Bechtolsheim, Sun Microsystems

   The DECstation 3100
   Mike Nielsen, DEC

   A Multiprocessor Graphics Workstation Architecture
   Forest Baskett, Silicon Graphics

   The XD88 Series Graphics Workstations
   John Theus, Tektronix

   The AViiON workstation
   Robert Cousins, Data General

   A Chip Set for a MIPS-based Micro Channel System
   Skip Smoot, Bull Micral of America

   Panel: Trends in Workstation Design
   Above speakers plus Larry Siebert (Opus Systems)

Lunch: The First Annual Microprocessor Report Awards
Nick Tredennick, Master of Ceremonies

RISCs for Embedded Control

   A Superscalar Implementation of the 80960
   Steve McGeady, Intel

   The Next Generation of the 29000 Family
   Bob Perlman, AMD

   A MIPS Processor for Embedded Control
   John Mick, IDT

   An Acorn-based Microcontroller
   Ron Cates, VLSI Technology

   Panel: The Future of RISC in Embedded Control
   Above speakers plus Gene Hill (LSI Logic)

Expanding the Microcontroller Range

   The 68332: A 68020-Based Microcontroller
   John Vaglica, Motorola

   The 96002 Floating-Point DSP
   Garth Hillman, Motorola

   The 34020 Graphics System Processor
   Karl Guttag, Texas Instruments

Embedded Control Designer Perspectives

   Evaluating processors for laser printer controllers
   David Wurmfeld, Phoenix Technologes

   High-Performance Networking Interfaces
   Steve Holmgren, CMC

   Panel: Selecting an Architecture for Embedded Control
   Above speakers plus Jonathan Levy (National) and George
   Nicol (Silicon Composers)

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