[news.announce.conferences] CFP: workshop on algorithms and parallel VLSI architectures

kroon@alice.UUCP (Peter Kroon) (11/08/89)

                          International Workshop on

                  ALGORITHMS AND PARALLEL VLSI ARCHITECTURES

                             June 10--16, 1990
                           Pont-a-Mouson, France


                      Announcement and Call for Papers

  CONFERENCE COMMITTEE

  Ed Deprettere                          Patrick Dewilde
  Dept. of Electrical Engineering        Dept. of Electrical Engineering
  Delft University of Technology         Delft University of Technology
  Delft, The Netherlands                 Delft, The Netherlands
  email: ed@dutentb                      email: dewilde@dutentb

  Thomas Kailath                         Sun-Yuan Kung
  Information Systems Laboratory         Dept. of Electrical Engineering
  Stanford University, USA               Princeton University, USA
  email: tk@isl.stanford.edu             email: kung@princeton.edu

  C.V.K. Prabhakara Rao                  Yves Robert
  Dept. of Electrical Engineering        Laboratoire LIP/IMAG
  Drexel University                      Ecole Normale Superieure de Lyon
  Philadelphia, USA                      Lyon, France
  email: rao@drexel                      e-mail: yrobert@ensl.ens-lyon.fr

  The goal of the International Workshop on Algorithms and Parallel VLSI
  Architectures is to bring together researchers, active in the fields
  indicated below. The workshop is sponsored by EURASIP in cooperation with
  the IEEE.

                                COURSES

                Schur's Algorithm and its Applications
                Large Scale Modeling
                Multiscale Signal Processing
                Solving Large Systems of Linear Equations
                Array Forms of Fast Signal Processing Algorithms
                Architecture Design

                                WORKSHOPS

    Signal Estimation                Architectures for Control & Communications
    Eigenvalues and Singular Values  Systolic Architectures
    Adaptive & Orthogonal Filtering  Artificial Neural Nets
    Modeling with Finite Elements    Microcoded Architectures
    Computer Graphics                Video Architectures


  The courses will be given by eminent lecturers in the field (names
  yet to be announced).  The workshops will consist of both plenary talks
  by invited speakers and poster presentations.
  At this moment, papers that contribute to the poster sessions are
  solicited.  Authors are invited to submit four copies of a 4-page summary
  of the paper to the workshop secretariat for review.
  Papers will be severely reviewed -- the number of accepted papers is limited.
  Authors of accepted papers will be asked to prepare a version for publication.
  Please note that participation in the workshop is open to authors only.


                           AUTHORS' SCHEDULE

	      Submission of 4-page summary: Februari 19, 1990
	      Notification of Acceptance:   March 30, 1990


                         WORKSHOP SECRETARIAT

			Alle-Jan van der Veen
			Dept. of Electrical Engineering
			Delft University of Technology
			2628 CD  Delft
			The Netherlands
			  email: allejan@dutentb
		          tel.: +3115781442
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