nagy%warner.hepnet@LBL.ARPA (Frank J. Nagy/VAX Guru) (10/06/87)
>Correct me if I am wrong: Aren't the "interlocked" instructions such as >adwi, bbssi, bbcci only really useful on the obsolescent vax 11/782 shared >memory? Don't all instructions--except for those which trash registers (which >are also used to save the context of the executing instruction) like movc-- >non-interruptable. I understood that unless you had the 11/782 multiport >memory, bbcc was as good as bbcci. Or is there still requirement for special >interlocking when you have multi processors such as the 8800? In general, what you say is true on a single processor machine like the 8250 (for instance). In that case the BBCC and BBCCI are identical; the need for the interlocking appears on any multi-processor machine (the 8350, 8800 or any VAX with a CI port). The interlocked instructions insure that the memory is modified by a read-modify-write type of cycle so that no other bus master can access the same memory location between the time the read starts and the write finishes. Consider the 8250/8350 systems for instance (this may be a bit of fantasy, I'm not 100% sure how the processors and the BI interact but am conjecturing based on my experience with other computers, including Digital's) where the memory is on the BI bus and the processor must execute BI cycles to access memory. The BBCC instruction might require two separate BI cycles to first read the memory and a second to write the memory. In the 8350, while CPU #1 is busy after the read cycle but before the write cycle, CPU #2 could access or write to the same memory location. The BBCCI instruction would use an interlocked bus cycle to prevent such an occurence. Thus CPU #2 would see the location *as modified* by CPU #1. Another point about the interlocked instructions is that they insure that the cache memory is either bypassed or insure that the caches on the other processors in the system are flushed of any (now) stale contents of the modified memory location. The point about the CI port... intercommunication between the CPU and the CI port is via a set of command and response queues. The CPU manipulates the queues with the interlocked self-relative queue instructions. The CI port (microprocessor) is able to handle virtual addresses (the pages must be in memory, but the microP can make the virtual to physical conversion itself) and self-relative queues. = Frank J. Nagy "VAX Guru" = Fermilab Research Division EED/Controls = HEPNET: WARNER::NAGY (43198::NAGY) or FNAL::NAGY (43009::NAGY) = BitNet: NAGY@FNAL = USnail: Fermilab POB 500 MS/220 Batavia, IL 60510