schwarze@isaak.uucp (Jochen Schwarze) (07/28/90)
We are currently porting the MIT X11R4 Sample Server to a new
architecture and have some problems getting the cfb routines to work
correctly.
The machine has a 68020 cpu and a Hitachi 63484 ACRTC graphics
controller. This controller uses 16 bit words, LSB first. The frame
buffer memory is shared with the cpu (32 bit, MSB).
We have first tried to keep PPW == 4 and swapped the various mask
values (0x00112233 -> 0x11003322). But the bit shifting routines
still assume the bytes to be contigious in a word. We suppose this
dependency would be very hard to eliminate.
We have then tried to define the following:
PPW 2
PLST 1
PIM 0x01
PWSH 1
BITMAP_BIT_ORDER LSBFirst
BITMAP_SCANLINE_UNIT 16
IMAGE_BYTE_ORDER LSBFirst
This still imposes lots of problems as all the 8-bit routines that
rely on PPW == 4 are no longer usable.
We would gratefully appreciate any hints that could help us with the
porting work.
Thank you very much.
--
Jochen Schwarze Domain: schwarze@isa.de
ISA GmbH, Stuttgart, West Germany UUCP: schwarze@isaak.uucp
Bang: ...!uunet!unido!isaak!schwarzekeith@EXPO.LCS.MIT.EDU (Keith Packard) (07/28/90)
> The machine has a 68020 cpu and a Hitachi 63484 ACRTC graphics > controller. This controller uses 16 bit words, LSB first. The frame > buffer memory is shared with the cpu (32 bit, MSB). If you look at the MFB code, you'll find that IBM has also designed brain-damaged hardware where the display doesn't match the CPU. To compensate for this, they byteswap for every shift operation to align things, shift, and byteswap back. You should be able to get some things working by abusing CFB in a similar manner. Note that this will cause your display to run quite a bit slower as a result. Perhaps you should redesign the hardware to have matching endian parts (I'm only partially kidding). But, you'll still have to hack the stippling code (including text) to arrange the stipples in the correct order. These changes should be reasonably localized to cfb8bit.c and cfb8bit.h. > PPW 2 > PLST 1 > PIM 0x01 > PWSH 1 This is definately wrong - PPW defines the number of pixels in a machine word. As you have 8-bit pixels on a 32-bit machine, PPW must be 4. Keith Packard MIT X Consortium
jfc@ATHENA.MIT.EDU (John Carr) (08/04/90)
A few months ago I made changes to cfb to run on the depth 2 display on the
NeXT system. I never finished input/event handling for the server port, but
the drawing routines were working fine when I stopped. I can make my changes
available by email or anonymous ftp.
These changes are relative to an earlier version of the cfb code (I stopped
work in mid-march); I haven't checked to see how much work it would take to
bring it up to date.
--John Carr (jfc@athena.mit.edu)