curtis@cit-vax.Caltech.Edu (shan Curtis) (05/24/87)
References: If I'm using DRAMS (Fujitsu MB81257-12) only in Read, Write and CAS-before RAS refresh, it would appear from looking at the timing diagrams, that the Q line (data out)is always hi-Z until read cycles. Is it ok to connect the Q and D lines together and directly to the bus, thereby avoiding having to use buffers? Thanks for the help in advance. Curtis ccl@juliet.caltech.edu curtis@cit-vax.caltech.edu
grr@cbmvax.cbm.UUCP (George Robbins) (05/24/87)
In article <2804@cit-vax.Caltech.Edu> curtis@cit-vax.UUCP (Curtis Ling) writes: > > If I'm using DRAMS (Fujitsu MB81257-12) only in Read, Write and CAS-before > RAS refresh, it would appear from looking at the timing diagrams, that > the Q line (data out)is always hi-Z until read cycles. Is it ok to connect > the Q and D lines together and directly to the bus, thereby avoiding having > to use buffers? Thanks for the help in advance. > > Curtis ccl@juliet.caltech.edu As a general rule, you can tie data in and data out together as long as your write signal is asserted before CAS. Whether you can tie the rams directly to a bus is more complicated, but as long as you understand that CAS is, in effect, an output enable signal, you can avoid conflicts. If you are planning on connecting to some kind of "external" microcomputer bus, you will probably need some kind of buffers for reliable operation. Also, do not neglect series termination resistors on address and control lines, and proper layout and decoupling. DRAM's *can* be a real pain in the ass unless treated with the proper degree of respect. -- George Robbins - now working for, uucp: {ihnp4|seismo|rutgers}!cbmvax!grr but no way officially representing arpa: cbmvax!grr@seismo.css.GOV Commodore, Engineering Department fone: 215-431-9255 (only by moonlite)
phil@amdcad.AMD.COM (Phil Ngai) (05/26/87)
In article <2804@cit-vax.Caltech.Edu> curtis@cit-vax.UUCP (Curtis Ling) writes: > >If I'm using DRAMS (Fujitsu MB81257-12) only in Read, Write and CAS-before >RAS refresh, it would appear from looking at the timing diagrams, that >the Q line (data out)is always hi-Z until read cycles. Is it ok to connect >the Q and D lines together and directly to the bus, thereby avoiding having >to use buffers? Thanks for the help in advance. This kind of thing can work, as I have done it in a product. Note, that one of the claimed features is "Common I/O capability using 'Early Write' operation". Some important considerations are 1) are you doing early write cycles? If you are doing late writes, the RAM will probably experience a bus collision with the device doing the write until you assert *W. This is because the RAM doesn't know you're not doing a read cycle until *W is activated. 2) Also check the load capacitance presented to each of the drivers on the data bus. DRAMs generally drive 100 pF and present about 7 pF on each of D and Q. 3) All the usual stuff about good bypassing, transmission line effects, motherhood and apple pie. If you only have 16 devices or so you can afford to be somewhat sloppy (that's the number I used and the signals were super clean) and with 64 you have to be more careful. There are special RAM drivers with series termination resistors in the IC, these provide faster drive with more symmetric rise and fall times. Look for the 2965 or 2966. What is this doing in rec.aviation? -- Phil Ngai, {ucbvax,decwrl,allegra}!amdcad!phil or amdcad!phil@decwrl.dec.com