rvk@att.att.com (12/21/88)
"Fujitsu Microelectronics Inc. has served notice that it intends to be to be top dog in the Sparc family. Using Wescon as its forum, the San Jose, Calif. company last month said it would come to market in mid-1989 with a 64-bit superset of the Sparc architecture, one that it says will be the first commercial device to attain the theoretical optimum of reduced-instruction-set-computer architecture: one instruction per cycle. Among the key developments planned is a unique microarchitecture for Sparc processors that contains proprietary pipeline concepts that are optimized for critical load/store and branch instructions. Fujitsu executive believe the load/store function is the key to accomplishing one-instruction-per-cycle RISC architecture. Fujitsu's next-generation Sparc will also have a dual 64-bit data nad instruction bus architecture. In addition, the family will have new fast cash-memory chips and a memory-management unit. The new Sparc-H series was described to a Sparc vendors' group just two days before the Wescon disclosure because 'we just want them to know that we had a development that would make their products obsolete,[!!]" says Tim B. Smith, vice president and general manager of Fujitsu's Advanced Products Division. Other manufacturers of Sparc-based processors are Bipolar Integrated Technology, Cypress, LSI Logic, and Texas Instruments. One of the primary benefits of Fujitsu's development is that with absolutely no improvements in process technology or clock rate, performance will be boosted by about two thirds. So where the current 32-bit Fujitsu Sparc implementation, the S-25, provides 15 million instruction per second at a clock speed of 25 MHz (1.66 cycles per instruction), with the one-to- one correspondence between cycle time and instruction execution, a 25 MHz Sparc-H implementation will operate at 25 mips. Existing RISC implementations from other companies, says Smith, with cycle-per-instruction ratings as high as 2.6, would require new processes to achieve clock rates of 30 to 40 MHz for comparable mips ratings. Although Fujitsu says there is a 64-bit internal data bus, it has not disclosed any other parts of the processor as 64 bits wide. However, the most fundamental design change is a shift from the present architecture to a Harvard-style implementation with separate instruction and data paths. By providing a separate cache/memory management unit for each bus, the bus bandwidth of the processors is increased. This technique can be enhanced by doubling each bus from 32 to 64 bits." -Electronics, Dec. 1988
daw@sun.com (Doug Ward) (12/31/88)
Boy, I hate it when articles get the facts twisted up like that! The Fujitsu chip is not a 64-bit superset of the SPARC architecture. It is a SPARC chip (all the same instructions and registers), with 64 bit data and instruction pathways. The Scalable Processor Architecture for RISC Computers (SPARC) very carefully did *not* specify any details of the interface between the inside (instruction set, registers) and the outside (memory access, cache, mmu). One of the things that makes it "scalable" is that the "Harvard Architecture" is one of the things you can invest space and money in to make a high speed implementation. The Electronics article makes it sound like Fujitsu is somehow breaking away from SPARC. They are in fact adhering to the architecture fully. The Sparc-H series will be code compatible with all the other SPARC implementations. Only the hardware is different. -daw