djones@decwrl.dec.com (Dave Jones) (05/23/89)
One more time on the matter of loading instructions into SPARC memory and then branching to them. I think I have the low-down on it now. What prompted all this is to be found in Chapter 4, page 39 of the SPARC architecture manual: Load and store instructions are the only instructions that access memory and registers external to the processor. They generate a 32-bit byte address. In addition to the address, the processor always generates an _address_space_identifier_, or _asi_. The address space identifier generated by the processor is made available to the external system ... It goes on to identify asi 8 as the user instruction-space, and asi 10 as the user data-space. According to several people who have been good enough to send me responses, the existing Sun SPARC machines do not use the _asi_ to distinguish address-spaces, but instead they use one address space for both instructions and data. The MMU simply ignores the asi. One correspondent tried an experiment, and was able to write instructions to memory and then execute them. Another indicated that Saber-C works that way on the SPARC. So it appears that in current systems at least, the asi is a red herring. I hope to have a SPARC-Station soon. When I get it I'll be able to verify.