emrath@uiuccsb.UUCP (07/02/83)
#R:ccvaxa:15200007:uiuccsb:14900001:000:1201
uiuccsb!emrath Jul 1 18:16:00 1983
The question about nested interrupt levels prods me to ask a
related question that I have wondered about before.
Can somebody explain the following code in "locore.s" at "alltraps:"?
alltraps:
....
mtpr $HIGH,$IPL # <<< WHY IS THIS HERE???
rei
This mtpr instruction raises the priority level to the max, so that the rei
won't fail by trying to go to a higher priority level. When I first read that
the rei instruction checked for this, I thought it was really smart, for it
helps the system programmer find buggy code which improperly handles the
priority level. Any interrupt/exception routine that LOWERS the priority
below the interrupted level had better know damn well what it is doing.
I've seen systems that would crash or hang once every 3.2 blue moons, only
to find that some interrupt routine was lowering the priority, allowing
re-entry or corruption of data structures (possibly of some unrelated device
handler).
The mtpr instruction should not be there. Any routine that lowers the
priority should explicitly raise it again, and the reason for
doing so should be WELL commented.
Perry Emrath, Univ. of IL
...{decvax|inuxc}!pur-ee!uiucdcs!emrath
emrath.uiuc@rand-relaybobvan@ccvaxa.UUCP (07/02/83)
#N:ccvaxa:15200007:000:1179
ccvaxa!bobvan Jun 30 22:15:00 1983
We're porting 4.1c to non-DEC hardware where it is expensive (time
wise) to emulate the DEC spl instruction (you have to wait for the main
cpu to go interrupt several I/O processors and wait for them to ack).
The new machine is very fast otherwise, including instructions that
just plain disable and enable all interrupts (interrupt requests are
queued when disabled). We are in the initial design phases of the
port, and are considering replacing spl0() calls with an enable
interrupt instruction, and all other spl?() calls with a disable
interrupt instruction.
My question is: Do anyone know of places in the kernel where this will
cause us trouble? That is, does the kernel RELY on having discrete
nested interrupt levels, or is it just using this handy facility built
into DEC hardware? I think we can nest the two software interrupt
levels (softclock and network) easily, but it'd sure be nice if we can
lump all of the "hardware" spl()'s into one level that is either
enabled or disabled.
As usual, please reply directly to me, and I'll summarize if interest
warrants.
Bob Van Valzah ...decvax!pur-ee!uiucdcs!ccvaxa!bobvan
Compion Corp. (217) 384-8587