jcd@dopsa.att.com (Jack C Dixon) (11/30/90)
On page 88 of the Nov 12 issue of Unix Today there is an article titled
"Sun Rivals Blast SPARCstation 2". I'll list a few quotes from the
article and hopefully someone out there familiar with the SPARC
architecture will comment on their accuracy.
"Sun Microsystems' competitors showed surprising unanimity in the nature
of their attacks on the SPARCstation 2 last week, saying that the product
demonstrates that the SPARC chip has reached its technological limit.
"... workstation manager at DEC, said that for Sun to achieve comparable
compute performance to DEC's newest workstation, it had to turn the
performance up to 40 MHz, a very high speed ... That puts the SPARC
technology near the high end of its performance capabilities.
"... program manager at HP/Apollo, noted that the SPARC chip appears to
have reached its limits to growth. 'They're running that thing at 40 MHz
generating 28 MIPS. That's anemic. That's bad. That's terrible.' ...
'With Sun having that standardized SPARC, that hurt them. They can't
innovate, and that chip is not very efficient.'"
Jack Dixon, AT&T
{ ...!att!vogon!jcd, jcd@vogon.att.com }davecb@nexus.yorku.ca (David Collier-Brown) (12/08/90)
jcd@dopsa.att.com (Jack C Dixon) writes: | On page 88 of the Nov 12 issue of Unix Today there is an article titled | "Sun Rivals Blast SPARCstation 2". I'll list a few quotes from the | article and hopefully someone out there familiar with the SPARC | architecture will comment on their accuracy. | "... program manager at HP/Apollo, noted that the SPARC chip appears to | have reached its limits to growth. 'They're running that thing at 40 MHz | generating 28 MIPS. That's anemic. That's bad. That's terrible.' ... | 'With Sun having that standardized SPARC, that hurt them. They can't | innovate, and that chip is not very efficient.'" Interestingly enough, that was one of the myths attacked by Howard Lee of Sun when speaking at the University of Toronto last week. To oversimplify, he said that everyone was hitting technology limits with particular implementations/micro-archetectures. Their competitors using Harvard architectures were hitting limits around 25mhz, Sun were pushing it at 33mhz. The answers were simple: spend money. Sun was spending it on bi-cmos and multiprocessors (n <= 4) and other, longer-term experiments, plus shortening the time-to-system after first silicon, which they saw as a serious industry-wide problem. They had been spending it on ecl, but that looked like it would be overtaken by other technologies before it could get to market. David Collier-Brown, | davecb@Nexus.YorkU.CA, ...!yunexus!davecb or 72 Abitibi Ave., | {toronto area...}lethe!dave or just Willowdale, Ontario, | postmaster@{nexus.}yorku.ca CANADA. 416-223-8968 | work phone (416) 736-5257 x 22075
chuck@trantor.harris-atd.com (Chuck Musciano) (12/10/90)
> On page 88 of the Nov 12 issue of Unix Today there is an article titled > "Sun Rivals Blast SPARCstation 2". I'll list a few quotes from the > article and hopefully someone out there familiar with the SPARC > architecture will comment on their accuracy. What did you expect, a hearty round of congratulations? :-) Seriously, the comments from DEC and HP should be viewed as nothing more than attempts to defuse Sun's product announcement. While I cannot speak about specific technical details of SPARC and when the CMOS versions will tap out, it should be pointed out that other SPARC technologies are either shipping or on the way. FPS Computing is shipping ECL SPARC systems, and hopes to have 65 MHz, 60 MIPS chips available soon. Other vendors are working on superscalar SPARC architectures. SPARC is far from dead. I wonder why DEC didn't comment on the failure of MIPS to produce an ECL MIPS chip, leading to the cancellation of the DECStation 6000, and forcing DEC to turn to yet another architecture, its internal E-VAX architecture. There is plenty of innovation in the world of SPARC, thanks to the fact that Sun made SPARC available to many different silicon foundries. DEC cannot innovate on MIPS, since they don't control the company that makes the chips. SPARC innovation will occur as different companies try to offer better products to the SPARC system vendors. Chuck Musciano ARPA : chuck@trantor.harris-atd.com Harris Corporation Usenet: ...!uunet!x102a!trantor!chuck PO Box 37, MS 3A/1912 AT&T : (407) 727-6131 Melbourne, FL 32902 FAX : (407) 729-2537
elling@eng.auburn.edu (Richard Elling) (12/11/90)
jcd@dopsa.att.com (Jack C Dixon) quotes from UNIX!Today: > "Sun Microsystems' competitors showed surprising unanimity in the nature > of their attacks on the SPARCstation 2 last week, saying that the product > demonstrates that the SPARC chip has reached its technological limit. These people had a lot of fun stating that the 40 MHz SPARC was at it's technological limit. But what they fail to do is put it in the proper context. True, the Cypress CY601 Integer Unit (used in the 4/470, 4/490, SS-2) peaks at 40 MHz but it is *old* silicon. These parts have been available for at least a year and a half. We are just now beginning to see the next generation of SPARC chips become available such as the Solbourne chip used in the S-4000. As the competition heats up, and we see more and more clones, the chip manufacturers will rise to meet the demand of us power hungry users. Anyway, I thought the article was good for a deep-belly laugh :-) After all, they didn't say those nasty things about the SPARC architecture when the 4/490 came out... maybe because they didn't have a truly competitive machine at the time? Richard Elling Manager of Network Support Auburn University Engineering Administration Work: relling@eng.auburn.edu (205)844-2280 Play: relling@cup.portal.com AMPR.ORG: 44.100.0.72 (KB4HB)
hartzell@boulder.Colorado.EDU (George Hartzell) (12/14/90)
In article <733@brchh104.bnr.ca> chuck@trantor.harris-atd.com (Chuck Musciano) writes:
[...]
I wonder why DEC didn't comment on the failure of MIPS to produce an ECL
MIPS chip, leading to the cancellation of the DECStation 6000, and forcing
DEC to turn to yet another architecture, its internal E-VAX architecture.
[...]
MIPS didn't fail to produce an ECL MIPS chip (the R6000). They failed to
produce it in a high enough yield soon enough to satisfy DEC. MIPS is
shipping R6000 based systems (the 6280) and claims to have worked out the
production problems (time will tell...).
George Hartzell (303) 492-4535
MCD Biology, University of Colorado-Boulder, Boulder, CO 80309
hartzell@Boulder.Colorado.EDU ..!ncar!boulder!hartzellmash@mips.com (John Mashey) (12/17/90)
In article <744@brchh104.bnr.ca> elling@eng.auburn.edu (Richard Elling) writes: Some of this article was pretty silly, as was the title. >... the next generation of SPARC chips become available such as the >Solbourne chip used in the S-4000. Please see the performance level delivered by that chip. I hear about 12 SPECmarks, @ 25/33 MHZ (I've heard both, so I'm confused), i.e., 60-70% of what a 25MHz R3000 delivers (and the cost of the R3000/R3010+cache+glue is something like $350; I've SEEN the Solbourne chip, and I rather doubt it costs less than that....) The interesting next SPARC will be the Sun/TI Viking. (personal opinion: most of the rest don't count; Viking is the one Sun is designing in and working on like crazy.) >Anyway, I thought the article was good for a deep-belly laugh :-) After >all, they didn't say those nasty things about the SPARC architecture when >the 4/490 came out... maybe because they didn't have a truly competitive >machine at the time? I have no idea what they were thinking. We of course didn't say anything, although the 490 & MIPS M/2000 are pretty much twins, except for the M/2000 doing a little better on multi-user performance, and the M/2000 shipped 1 year earlier... A more rational article in the first place would have said: 1) SS2 looks OK, but it's essentially playing catchup with DEC 5000s and MIPS Magnums (i.e., it's a little faster, but not much), and the cost/performance is no better, in practice. [Remember when Sun was always first out the door, and almost always had an edge in cost/performance?) The SS2 is a good machine, but doesn't seem like anything special to me. (Unlike, the first SS1, which was a real breakthru at the time, especially in terms of packaging and low parts-count). 2) R3000As will be coming in machines soon: the first serious tuneup of many of the original circuits design in 1985 for 2mcron CMOS will let us get good yield @ 33MHz, and some faster. Given all of the usual numbers, 33MHz R3000As are about as fast as 50MHz Cypress SPARCs, and I think it is true that those will difficult, or at least expensive (need very special modules), but not impossible. Certainly, life will get tought for everybody, fairly soon, with the existing designs, which is why everyone is working on something different, of course:-) -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086