vanroy@ucbvax.berkeley.edu (03/19/91)
I am in the process of retargeting a compiler for the SPARC. I am building an instruction reordering stage. To achieve the best performance, I need information about the memory system and the pipeline structure of several implementations of the SPARC. The machines I am interested in are the SPARCstation 1+ and the SPARCstation 2. Does the machine have a cache? If so, what are its characteristics? What operations will insert a bubble, i.e. a no-op cycle, in the pipe? For example: How many cycles are needed to do a load and a store? Is there any advantage (apart from needing only a single instruction fetch) to the double-word loads and stores? Does using a register the cycle after it is loaded create a bubble? Does doing two loads or stores in sequence create a bubble? Thanks very much, Peter Van Roy Computer Science Division University of California, Berkeley vanroy@polaris.berkeley.edu
eric@uunet.uu.net (Eric Parker) (03/27/91)
Here is a program that I wrote to benchmark loads and stores on various machines. By inspecting the assembler output (cc -S option) I was able to determine that the Sun Sparcstation machines using the LSI chipset take 2 cycles for a cache hit read and 6 for a cache hit write. The read has no load delay slot (i.e. the processor is stalled while the cache system does the read). The write has one delay slot (so back to back writes take 6 clocks). Hope this helps. - Eric Paker (214) 985-2217 [[Ed's Note: Placed in archives on titan. -bdg]] FTP: Hostname : titan.rice.edu (128.42.1.30) Directory: sun-source Filename : ldstr.c Filesize : 7064 bytes Archive Server Address: archive-server@rice.edu Archive Server Command: send sun-source ldstr.c