yamauchi@cs.rochester.edu (Brian Yamauchi) (09/12/89)
Do the PDP-11 and the LSI-11 have the same instruction set and use the same opcodes? Our lab has a Unimation Puma whose VAL II controller is based on the LSI-11. Unfortunately all the LSI-11 assembly language manuals seem to have vanished from the face of the Earth. My list of phone numbers is starting to look like an FSM diagram (DEC XYZ Center: "No we don't know anything about that, but you could try the DEC XYZZY Center.") However, I was able to find a book which has a list of PDP-11 instructions and opcodes. Is it safe to assume that these are the same as for the LSI-11? If not, does anyone know whether the "LSI-11 Users System Guide" has what I'm looking for? (This was the only LSI-11 document the DEC people knew about, but they had no idea what it contains.) _______________________________________________________________________________ Brian Yamauchi University of Rochester yamauchi@cs.rochester.edu Computer Science Department _______________________________________________________________________________
frank@croton.dec.com (Frank Wortner) (09/12/89)
In article <1989Sep11.221225.17780@cs.rochester.edu>, yamauchi@cs.rochester.edu (Brian Yamauchi) writes: > Do the PDP-11 and the LSI-11 have the same instruction set and use the > same opcodes? > Yes, they do. However, there are some variations from model to model. 11/03s don't support floating point, 11/23s support memory management hardware, etc. The simpler, "core" instructions are the same. Frank
dheap@gara.une.oz (Dave Heap PSYS) (10/10/89)
In article <1989Sep11.221225.17780@cs.rochester.edu> yamauchi@cs.rochester.edu.UUCP (Brian Yamauchi) writes: >Do the PDP-11 and the LSI-11 have the same instruction set and use the >same opcodes? > Basically, yes. All PDP11s (including the LSI11) support the basic PDP11 instruction set. A few exceptions such as SOB, MARK, RTT & SXT are not supported on all. Optional instructions such as EIS & floating point depend on the CPU &/or its fitted options. Minimal differences exist between CPUs for unusual instructions such as MOV R1,(R1)+ where autoincrementing may take place before or after R1 is read, depending on the processor. In general, you shouldn't have any problems. If you really need it, I have documentation of PDP11 family differences. (Sorry about the late reply, I mailed this direct, went on holiday & returned to find it had bounced.) -- Dave Heap ACSNET: dheap@gara.une.oz Psychology Department, UUCP: ...!uunet!munnari!gara.une.oz!dheap University of New England, ARPA: dheap%gara.une.oz@uunet.uu.net Armidale NSW 2351, Australia