goehring@ai.mit.edu (Not Marc Spencer) (02/12/91)
The _VAX Architecture Reference Manual_ specifies that SCB vector 00 is for a "passive release" interrupt. What is a "passive release", what causes one, what is the OS expected to do with one of these, and what parameters are pushed on the stack? Any reasonable answers appreciated; pointers to answers somewhat less so as I have minimal access to documentation. I have no experience with any of the VAX bus architectures (i.e. I'm interested mainly from a software viewpoint), so forgive me if this is an obvious question. -- Help stamp out vi in our lifetime! Scott Goehring goehring@ai.mit.edu On exile in Indianapolis, IN -- Help stamp out vi in our lifetime! Scott Goehring goehring@ai.mit.edu On exile in Indianapolis, IN
terry@spcvxb.spc.edu (Terry Kennedy, Operations Mgr.) (02/12/91)
In article <GOEHRING.91Feb11202106@ai.mit.edu>, goehring@ai.mit.edu (Not Marc Spencer) writes: > The _VAX Architecture Reference Manual_ specifies that SCB vector 00 > is for a "passive release" interrupt. What is a "passive release", > what causes one, what is the OS expected to do with one of these, and > what parameters are pushed on the stack? In brief, when a device asks for the bus via interrupt request, but then decides to ignore the interrupt ack from the Unibus adapter. Thus, the ack progresses through the backplane. If no other device grabs it, it hits the terminator. Thus, no vector is passed to the processor, and you get the default vector. From an application point of view, you'll never see this. From the driver's point of view, it won't either (but it should avoid placing the hardware in a state where it will generate passive releases, as they delay bus operations. Terry Kennedy Operations Manager, Academic Computing terry@spcvxa.bitnet St. Peter's College, US terry@spcvxa.spc.edu (201) 915-9381
slsw2@cc.usu.edu (02/14/91)
In article <1991Feb12.044547.1097@spcvxb.spc.edu>, terry@spcvxb.spc.edu (Terry Kennedy, Operations Mgr.) writes: > In article <GOEHRING.91Feb11202106@ai.mit.edu>, goehring@ai.mit.edu (Not Marc Spencer) writes: >> The _VAX Architecture Reference Manual_ specifies that SCB vector 00 >> is for a "passive release" interrupt. What is a "passive release", >> what causes one, what is the OS expected to do with one of these, and >> what parameters are pushed on the stack? > > In brief, when a device asks for the bus via interrupt request, but > then decides to ignore the interrupt ack from the Unibus adapter. Thus, > the ack progresses through the backplane. If no other device grabs it, > it hits the terminator. Close, but no cigar. You see, the UNIBUS bus requests are really DMA requests. Once a device has been granted the UNIBUS, it can do anything it wants including giving a vector to the CPU; note that the CPU is a slave for this operation, not the master. If the UNIBUS device decides not to give the CPU a vector, the bus is released and everything goes on its merry way; on a PDP-11, the bus request is ignored and the CPU is not interrupted. VAXes view the interrupt acknowledge sequence kind of like a special type of read; the CPU asks the interrupting device for a vector. The CPU is the master for this operation and the slave must respond. If the UNIBUS device elects not to give a vector to the processor, the UNIBUS adapter will return a 0 to complete the transaction. -- =============================================================================== Roger Ivie 35 S 300 W Logan, Ut. 84321 (801) 752-8633 ===============================================================================
slsw2@cc.usu.edu (02/14/91)
In article <1991Feb13.131922.46862@cc.usu.edu>, slsw2@cc.usu.edu writes: > Close, but no cigar. You see, the UNIBUS bus requests are really DMA requests. > Once a device has been granted the UNIBUS, it can do anything it wants > including giving a vector to the CPU; note that the CPU is a slave for this > operation, not the master. If the UNIBUS device decides not to give the CPU > a vector, the bus is released and everything goes on its merry way; on a > PDP-11, the bus request is ignored and the CPU is not interrupted. Oh yeah. One thing I've always wondered but have never tried. What happens if a device grabs the UNIBUS with an NPR and then decides to give the processor a vector? Is it a non-maskable interrupt? Anybody ever tried it? -- =============================================================================== Roger Ivie 35 S 300 W Logan, Ut. 84321 (801) 752-8633 ===============================================================================