gene@zeno.mn.org (Gene H. Olson) (05/28/91)
Looking through all the documentation I have been able to find
on the MIPS processor (Including Gerry Kane's book) I haven't
found a rule about putting a branch in a branch delay slot.
There is a very definite rule about doing this in the SPARC
architecture, probably because its not very useful, and may
have terrible implications in restarting instructions and so on.
So I tried to figure why MIPS has not excluded this particular
combination. It has some very odd implications. For example,
consider the following code:
.set noreorder
x0: j x3 # 1
x1: j x2 # 2
x2: j x3 # 4
x3: j x4 # 3 6
x4: j x5 # 5 8
x5: j x6 # 7 10
x6: j x7 # 9 12
x7: nop # 11 13 14
x8: nop # 15
x9: nop # 16
The comments indicate the order in which the instructions
are fetched into the pipeline and presumably the order in
which they execute. As I understand it, the effect of a
jump instruction is to change the address where the next
instruction will be fetched into the instruction pipeline,
while the next instruction (already in the pipeline) executes.
clock fetch execute
0 x0 -
1 x1 j x3
2 x3 j x2
3 x2 j x4
4 x4 j x3
5 x3 j x5
6 x5 j x4
7 x4 j x6
8 x6 j x5
9 x5 j x7
10 x7 j x6
11 x6 nop
12 x7 j x7
13 x7 nop
14 x8 nop
15 x9 nop
16 x10 nop
So it looks worthless, right? Well, it does have one
very interesting side effect. Some machines have an "execute"
instruction used to execute a single instruction out of sequence.
Well, using this trick, the MIPS processor also has one.
Consider the following code to execute the instruction at
address "target".
.set noreorder
x0: j target
x1: j x2
x2: nop
.set reorder
This case executes as follows:
clock fetch execute
0 x0
1 x1 j target
2 target j x2
3 x2 (instruction at target)
4 nop
So it seems the MIPS architecture, like the IBM 360,
does have an execute instruction.
exec target
Can be recoded as:
.set noreorder
j target
j .+4
.set reorder
So, you MIPS software development guys, how about you put it
in the assembler?
_________________________________________________________________________
__
/ ) Gene H. Olson gene@zeno.mn.org
/ __ _ __ _
(__/ _(/_//_(/_ gene@digibd.comherod@convex.com (Cliff Herod) (05/29/91)
In article <1991May27.184311.11596@zeno.mn.org> gene@zeno.mn.org (Gene H. Olson) writes: >Looking through all the documentation I have been able to find >on the MIPS processor (Including Gerry Kane's book) I haven't >found a rule about putting a branch in a branch delay slot. > Actually, the MIPS R-series Architecture document says: 2.7. Jump and Branch Instructions (may be number differently in other eds.) All jump and branch instructions are implemented with a delay of exactly one instruction. That is, the instruction immediately following a jump or branch (i.e. occupying the "delay slot") is always executed while the target instruction is being fetched from storage. It is not valid for a delay slot to be occupied itself by a jump or branch instruction; however this error is not detected, and the results of such an operation are undefined. > >So, you MIPS software development guys, how about you put it >in the assembler? What happens to your trick when the R4000 comes along with three delay slots?
craig@netcom.COM (Craig Hansen) (05/29/91)
In article <1991May27.184311.11596@zeno.mn.org>, gene@zeno.mn.org (Gene H. Olson) writes: > Looking through all the documentation I have been able to find > on the MIPS processor (Including Gerry Kane's book) I haven't > found a rule about putting a branch in a branch delay slot. > > There is a very definite rule about doing this in the SPARC > architecture, probably because its not very useful, and may > have terrible implications in restarting instructions and so on. > > So I tried to figure why MIPS has not excluded this particular > combination. The sequence you describe will work on an HP-PA (Precision, Spectrum) machine, but not a MIPS machine. The reason is will not work is that I only put one exception PC on the MIPS architecture, where the HP-PA has a queue of PC. This means that if an exception were to occur between the two adjacent branches, the machine state cannot be recreated after handling the exception. This includes I/O interrupts, so in general, two adjacent branches do not produce an architecturally definite result. Also, the target of a conditional branch is computed via an offset from the address of the dynamically following instruction, so placing a conditional branch in a branch delay slot is a tricky proposition. The only potentially safe combination is to place a conditional branch in the delay slot of another conditional branch, provided that the conditions are mutually exclusive. I don't recall clearly, but even this combination may have been excluded via the ReservedInstruction exeception...if not, perhaps it should! Regards, Craig Hansen craig@microunity.com