[comp.sys.dec] Caching Turbo Channel access ??

mxm@manta.mel.dit.CSIRO.AU (Mark Makies) (06/26/91)

Is it possible to cache I/O access from the Turbo channel
in a DEC Station 5000/200?
My main concern is to whether the hardware allows this.
If it is possible what modifications may have to be made
to the kernel?

Thanks,

Mark Makies       mark.makies@mel.dit.csiro.au
Digital Systems and Computer Engineering Group
Royal Melbourne Institute of Technology, Australia 

santiago@lerad.pa.dec.com (Ed Santiago) (06/26/91)

mxm@manta.mel.dit.CSIRO.AU (Mark Makies) writes:
>Is it possible to cache I/O access from the Turbo channel
>in a DEC Station 5000/200?
Sorry, the hardware does not allow it.

^E -- ex-DS5000 firmware type
Ed Santiago                                      santiago@decwrl.dec.com
DEC Workstations Systems Engineering             ..!decwrl!santiago

santiago@lerad.pa.dec.com (Ed Santiago) (06/27/91)

santiago@lerad.pa.dec.com (Ed Santiago) writes:
>mxm@manta.mel.dit.CSIRO.AU (Mark Makies) writes:
>>Is it possible to cache I/O access from the Turbo channel
>>in a DEC Station 5000/200?
>Sorry, the hardware does not allow it.
I've been asked to clarify this a little bit.  

My interpretation of this question was "is it possible to access device
registers on a TURBOchannel option via cache space?", eg, something like:

	volatile unsigned long *CSR = <something-in-cached-space>;

The answer to this is no -- the DS5000 hardware does not support it (for
those, like me, that always ignore "unsupported" -- it doesn't work either).

However, another interpretation of the question might have been "does
TURBOchannel allow DMA into cached pages in RAM?".  The answer to this
is "well, sort of".  TURBOchannel options may perform DMA anywhere in
system memory.  However, DMA transfers do *not* go through the cache,
so if a transfer occurs to a page that is currently cached, the cache
will not know about it and keep presenting stale data to the CPU.

Hope this helps,

^E -- ex-DS5000 firmware type
-- 
Ed Santiago                                      santiago@decwrl.dec.com
DEC Workstations Systems Engineering             ..!decwrl!santiago

slsw2@cc.usu.edu (06/27/91)

In article <1991Jun26.180424.27695@pa.dec.com>, santiago@lerad.pa.dec.com (Ed Santiago) writes:
>   TURBOchannel options may perform DMA anywhere in
> system memory.  However, DMA transfers do *not* go through the cache,
> so if a transfer occurs to a page that is currently cached, the cache
> will not know about it and keep presenting stale data to the CPU.

Actually, the TURBOchannel spec doesn't *forbid* DMA from going through the
cache, it's just that current implementations don't. That's what I like about
the TURBOchannel spec: carefully designed to be vague in all the right places
(example: "memory access latency; may be many t3 cycles" on pg. 7; you could
pipe TURBOchannel out an RS-232 port and not violate that...).

Roger Ivie
slsw2@cc.usu.edu