gibson@unc.UUCP (02/14/87)
In implementing a wavetable oscillator, I can think of 2 major ways
to control frequency (with some help from Computer Music Journal)
(3 ways, really, since the second involves a decision which radically
affects the implementation). If you can of ways other than these, or
if you have ideas about these, please let me know.
1) Output one sample per clock period; control the clock period with
a programmable divider to achieve the required 9 or 10 octaves of
control. The fundamental output frequency is f(clk)/((divisor)*(tablelength)).
A counter or shift register can be used to address the table.
2) Use a 'fixed-point' phase register to address the wavetable;
frequency is specified by d(phase)/dt (phase increment) in a register
which is repeatedly added to the current phase.
For convenience, I'll call the difference between 2 successive addresses
'1 degree'; e.g. a 10-bit address is used on a 1024-degree table.
The phase has p bits, (f) of which are fraction (e.g. 20-bit phase with
12 fraction bits for 256-degree wavetable).
A choice must be made about the size of the phase increment:
a) (phase increment) <= 1 degree
This implies
1) The table can have harmonics up to (tablelength/2)*fundamental.
2) Only (fundamental) frequencies lower than f(clk)/tablelength
are output.
b) (phase increment) <= (tablelength)/2 degrees
This implies
1) Spurious/alias frequencies may be output depending on the
actual phase increment (when > 1) and the harmonics
represented in the table.
If no spurious frequencies are to be generated, the table
must contain only the fundamental sinusoid.
2) Fundamental frequencies up to f(clk)/2 are output.
This scheme can be implemented as follows:
(p or f bits)
phase increment ------
| | |
v v |
(p-bit) adder |
| |
v |
current phase | (p bits)
| |
|-------
|
v
(p-f bits, i.e. integer part of phase
to be used as wavetable address )
Fundamental frequency of the output can be calculated using
f(aud) = f(clk) * (phase increment)/(table length)
Hz Hz (degrees) (degrees)
where there is 1 addition per cycle of f(clk).
I think (2) allows easier modulation of the output frequency, since
the phase increment can be modulated by including another adder stage.
Bill Gibson
gibson@unc ...[akgua,decvax,philabs]!mcnc!unc!gibson