tomk@intsc.UUCP (Tom Kohrs) (11/18/86)
In article <1295@hoptoad.UUCP>, John Gilmore writes: > In article <400@intsc.UUCP>, tomk@intsc.UUCP (Tom Kohrs) writes: > > ... architectures that Intel is selling (ie. 286,386, 586, and 786)... > > ...the 486 and beyond... > > Sounds good to me. Tom, can you start with a summary of the architecture > of each of these chips? What follows is the 5 minute summary of the intel product line (at least the x86 part). 80286. The 286 is a 16bit CPU with 4 data registers, 4 address registers, and 4 segment pointers. The part has an internal and external 16 bit data path, a 30 bit virtual address and 24 bit physical address path. The conversion from the 30 bit vitrual address to the 24 bit external address is accomplished by a segmentation mechanism. (flame throwers at the ready) The segmentation unit used a segment pointer register to index a table that contained a the 24bit segment base address a 16bit segment size constant and a type specifyer. Offset in the segment are calculated using an effective address that is the sum of up to two index registers and a displacement. The internal architecture consists of four independant units: Bus interface, Prefetcher, Execution, and Segmentation. Each unit works as part of a pipe line through the cpu. The instruction set uses byte aligned opcodes and data types. The chip will also execute the 8086 instruction set and addressing mechanism when in real mode (entered after reset). 80386 The 386 is a 32 architecture with 8 data/address registers and 6 segment pointers. The data path is 32 bits internal and external. Addressing is done with a 46bit virtual, 32 bit logical and physical paths. The virtual to logical convertion is done with a sementation mechanism similar to the 286. The difference being 32 bit base addresses and 4Gigabyte segment lengths. The effective address calculation for offsets into the segment are the sum of any two of the 32 bit registers and a displacement. Optionally one of the registers can be scaled by 2, 4 or 8. Conversion of logical to physical addresses are accomplished by a two tier paging unit that has a fixed 4K page size. The internal structure of the 386 consists of 6 units: Bus interface, Prefetch, Instruction, Exectuction, Segmentation, and Paging. The Instruction unit takes the byte aligned opcodes and converts them into internal microcode. The 386 will exectute 8086 code in real mode (after reset), or in vitual 86 mode. The instruction set is opcode compatable with the 286 and will execute 286 protected mode code directly. 80486 The 486 is the follow on processor to the 386. It will be object code compatable to the 386 and a lot faster (I had better shut up before I get in trouble). 82586 This is the Ethernet controller chip. (Current versions have the bugs out). This chip will do the functions of the data link layer of the ISO model. The part will work on either an 8 bit or 16bit bus. It contains a built in DMA controller that moves packets to and from the net with little CPU overhead. 82786 The 82786 is a high performance graphics display controller. The 786 has both a fast drawing engine and a display controller that supports hardware window functions. The part uses either an 8 bit or 16 bit cpu interface and allows complete cpu access to the graphics memory. The resolutions supported with full windowing features include 640x480x8bpp to 1Kx1Kx2bpp. With video RAM's the display controller will produce displays upto 1900x1900x8 bpp without the windowing features. This is breif but probably already too long for most of the net. More can be added later as interest in each warrants. Reference literature: Intel Microsystems Components Handbook P/N 230843 Intel Microcommunications Handbook P/N 231658 82786 CHMOS Graphics Coprocessor Data sheet P/N 231676 Literature may be ordered through : Intel Literature Sales P.O. box 58130 Santa Clara, Ca 95052-8130 (800) 548-4725 or contact your local intel sales office. -- ------ "Ever notice how your mental image of someone you've known only by phone turns out to be wrong? And on a computer net you don't even have a voice..." tomk@intsc.UUCP Tom Kohrs Regional Architecture Specialist Intel - Santa Clara