chris@cooper.UUCP (Chris Lent ) (12/03/86)
In article <9778@sun.uucp>, cmcmanis@sun.uucp (Chuck McManis) writes: > In article <83@reality1.uucp>, james@reality1.uucp (james) writes: > > Well, what's the most current rev. level for the 80286, ie, how recent > > should mine be to avoid all known bugs? Chip bugs are normally top secret, > > but I assume the the current chip rev. level isn't sensitive. > James, I don't think chip bugs are "top secret", ask your Intel sales rep > for an Errata sheet. They can also generally tell you the current rev > level or 'stepping' as the semiconducter trade likes to refer to it as. I'm was just wondering what are EASY (or relatively) ways to get mask-revision levels on various processors. From what I remember one of the long exception types on the MC68XXXX tacked on a mask revision level to the machine state. The idea here is that when a instruction is restarted, if the mask-revision level doesn't match, something happens (I believe an exception). The reason for this is in a multi-processor environment an interrupted instruction might be restarted on another processor. Does the 80XXX family have a similar capability? Also, from what I remember these long execption machine state dumps vary in length for the 68000, 010 and 020, and with a little tricky code it was possible to determine the processor type. Further, it can be VERY handy to be able to determine processor type from software in boot-up code. Late PDP-11 and all Vaxen (so far :-) have a simple instruction to grab processor type (and ECO level on the Vaxen). This allows code to be I) easily processor specific and II) allow marketing to enforce the "you MUST pay more for the same code on a larger machine in the XXXYYYZZZ series of COMPLETELY compatible machines" dictum. That's all Chris Lent ---- -- Chris Lent ihnp4!allegra!phri!cooper!chris