spalding@uiucdcsp.cs.uiuc.edu (04/04/88)
You could read the "current word count register", which goes to 0FFFFH at TC (terminal count). I don't know what peripheral card you're using here, but usually the peripheral senses the TC signal (from the 8237A, available on the I/O bus), so the peripheral card should know when TC is reached and would hopefully provide a status bit or interrupt signal. Note that when reading the 8237A's registers on the fly, you have to read them LSB, then MSB, and it is possible that a DMA cycle could occur in between, causing the values to be skewed. However, unless you are initially setting the word count to values with the most significant byte = 0FFH, you should be perfectly safe in reading the word count register and testing for 0FFFFH to detect TC. In general, when reading these registers on the fly, you need to disable interrupts, read the register twice, enable interrupts, and do some reasonableness testing on the results, on the assumption that, at worst, only one DMA cycle could have occured, so that only one of the readings would be skewed. BTW, the IBM RT also uses the 8237A, but the 64K boundary problem is avoided by allowing each 2K block within the 8237A's 64K address space to be individually mapped to a real page using "translation control words" (TCWs). -John W. Spalding spalding@p.cs.uiuc.edu